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TE3-MUX m13 multiplexer and ds3 framer peb 3445 e v2.1 data sheet, ds3, june 2001 datacom never stop thinking.
edition 2001-06-29 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 7/26/01. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
datacom TE3-MUX m13 multiplexer and ds3 framer peb 3445 e v2.1 data sheet, ds3, june 2001 never stop thinking.
for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com peb 3445 e revision history: 2001-06-29 ds3 previous version: preliminary data sheet 09.2000 page subjects (major changes since last revision) changed document to new documentation guidelines. 21 recommendation for demultiplexed bus operation added to signal lale. 55 added table content which was missing in previous version. 64f., 66f. 185ff., 188ff. figure 16 , figure 17 , figure 18 , figure 19 corrected. lbhe respectively lble were wrong in previous version. timings of lbhe in figure 24 and figure 25 redrawn. figure 27 added. merged timings for la and lbhe . timings of lble in figure 28 and figure 29 redrawn. figure 31 added. merged timings of la and lble . 84, 139 description of register bits sidle, saisa, rdc extended. 91, 101, 113, 118, 127, 151, 154 description of register bits od, xbit, gn, res, t1e1 corrected. 167, 179 major parts of register description (fhnd and phnd) rewritten. register fhnd: bits abort and xtf removed. register phnd: bit xtf removed. 177 removed register bit xra. 191 section ?dma interface signals? added. 204 rtd is updated with rising edge of rtc. this is corrected in figure 49 . some minor documentation updates (wording, syntax, ...). name change m13fx -> TE3-MUX. removed pef version. corrected table 27 "ds1/e1 receive data timing" on page 202 . changed figure 25 and 27. removed timing 35. changed timings 101,111,151,152,195,198. changed table 11. changed feac fhnd register to contain xtf bit.
peb 3445 e data sheet 5 2001-06-29 1 TE3-MUX overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.1 general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.1.1 m23 multiplexer and ds3 framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.1.2 m12 multiplexer and ds2 framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.1.3 bit error rate tester . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.3 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.1 pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3 local microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.5 test interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.6 power supply, reserved pins and no-connect pins . . . . . . . . . . . . . . . . . 30 3 general overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.2 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.1 remote and local loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.1.1 local loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.1.2 remote loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.2 b3zs code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.3 tributary mapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.4 m12 multiplexer/demultiplexer and ds2 framer . . . . . . . . . . . . . . . . . . . . 40 4.4.1 m12 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.4.1.1 synchronization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.4.1.2 multiplexer/demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.4.1.3 loopback control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.4.1.4 alarm indication signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.4.2 itu-t g.747 format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.4.2.1 synchronization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.4.2.2 multiplexer/demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.4.2.3 parity bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.4.2.4 remote alarm indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.4.2.5 alarm indication signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.5 m23 multiplexer and ds3 framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.5.1 m23 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.5.1.1 synchronization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.5.1.2 multiplexer/demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.5.1.3 x-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.5.1.4 alarm indication signal, idle signal . . . . . . . . . . . . . . . . . . . . . . . . . . 47
peb 3445 e data sheet 6 2001-06-29 4.5.1.5 loss of signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.5.1.6 performance monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.5.2 c-bit parity format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.5.2.1 synchronization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.5.2.2 multiplexer/demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.5.2.3 x-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.5.2.4 far end alarm and control channel . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.5.2.5 loopback control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.5.2.6 alarm indication signal, idle signal . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.5.2.7 loss of signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.5.2.8 performance monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.5.3 full payload rate format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.6 signalling controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.6.1 c-bit parity path maintenance data link channel . . . . . . . . . . . . . . . . 53 4.6.2 far end alarm and control channel (bom) . . . . . . . . . . . . . . . . . . . . . 53 4.6.3 signalling controller fifo operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.6.3.1 interrupt driven microprocessor operation . . . . . . . . . . . . . . . . . . . . 55 4.6.3.2 dma supported data transmission . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.7 test unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.8 interrupt interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5 interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.1 local microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.1.1 intel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.1.2 motorola mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.2 serial interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.2.1 ds3 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.2.2 ds1/e1 interface/ds3 system interface . . . . . . . . . . . . . . . . . . . . . . . . 69 5.2.2.1 ds1/e1 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.2.2.2 ds3 system interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.3 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6 reset and initialization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.1 chip initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.2 mode initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.1 register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.2 detailed register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.2.1 ds3 control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.2.2 ds2 control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 7.2.3 test unit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 7.2.4 test unit framer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 7.2.5 far end alarm and control channel (bom) registers . . . . . . . . . . . . 160
peb 3445 e data sheet 7 2001-06-29 7.2.6 c-bit path maintenance (hdlc) registers . . . . . . . . . . . . . . . . . . . . . 171 8 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 8.1 important electrical requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 8.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 8.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 8.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 8.4.1 local microprocessor interface timing . . . . . . . . . . . . . . . . . . . . . . . . 185 8.4.1.1 intel bus interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 8.4.1.2 motorola bus interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 8.4.2 dma interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 8.4.2.1 dma receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 8.4.2.2 dma transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 8.4.3 serial interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 8.4.3.1 ds3 serial interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 8.4.3.2 overhead bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 8.4.3.3 stuff bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 8.4.3.4 ds1/e1 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 8.4.3.5 ds3 system interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 8.4.4 jtag interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 8.4.5 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 9 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
peb 3445 e data sheet 8 2001-06-29
peb 3445 e list of figures page data sheet 9 2001-06-29 figure 1 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 2 typical ds3 channelized application . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 5 local loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 6 remote loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 7 tributary mapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 8 tributary mapper (transmit direction) . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 9 tributary mapper (receive direction) . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 10 interrupt driven reception sequence example (32-byte receive thresh- old) 56 figure 11 interrupt driven transmit sequence example . . . . . . . . . . . . . . . . . . . 57 figure 12 dma supported receive sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 13 dma supported transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 14 test unit access points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 15 pattern generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 16 intel bus mode (demultiplexed bus operation) . . . . . . . . . . . . . . . . . . 64 figure 17 intel bus mode (multiplexed bus operation) . . . . . . . . . . . . . . . . . . . . 64 figure 18 motorola bus mode (demultiplexed bus operation) . . . . . . . . . . . . . . 66 figure 19 motorola bus mode (multiplexed bus operation) . . . . . . . . . . . . . . . . 66 figure 20 receive overhead access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 21 transmit overhead access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 22 block diagram of test access port and boundary scan unit . . . . . . . 70 figure 23 input/output waveform for ac tests . . . . . . . . . . . . . . . . . . . . . . . . . 184 figure 24 intel demultiplexed bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 figure 25 intel multiplexed bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 figure 26 read, write control interval in demultiplexed bus mode . . . . . . . . . 187 figure 27 read, write control interval in multiplexed bus mode . . . . . . . . . . . 187 figure 28 motorola demultiplexed bus timing . . . . . . . . . . . . . . . . . . . . . . . . . 188 figure 29 motorola multiplexed bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 figure 30 read, write control interval in demultiplexed bus mode . . . . . . . . . 190 figure 31 read, write, ale control interval in multiplexed bus mode . . . . . . . 190 figure 32 dma receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 figure 33 dma transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 figure 34 clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 figure 35 ds3 transmit cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 figure 36 ds3 transmit data timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 figure 37 ds3 receive cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 figure 38 ds3 transmit overhead timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 figure 39 ds3 transmit overhead synchronization timing . . . . . . . . . . . . . . . 196 figure 40 ds3 receive overhead timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 figure 41 ds3 transmit stuff bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
peb 3445 e data sheet 10 2001-06-29 figure 42 ds3 receive stuff bit timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 figure 43 ds1/e1 transmit clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 figure 44 ds1/e1 transmit data timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 figure 45 ds1/e1 receive clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 figure 46 ds1/e1 receive data timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 figure 47 ds3 system clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 figure 48 ds3 system transmit data timing . . . . . . . . . . . . . . . . . . . . . . . . . . 203 figure 49 ds3 system receive data timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 204 figure 50 jtag interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 figure 51 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
peb 3445 e list of tables page data sheet 11 2001-06-29 table 1 m12 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 2 itu-t g.747 format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 3 m23 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 4 c-bit parity format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 5 data bus access 16-bit intel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 6 data bus access 16-bit motorola mode. . . . . . . . . . . . . . . . . . . . . . . . 65 table 7 register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 8 far end alarm and control transmit commands . . . . . . . . . . . . . . . 169 table 9 path maintenance transmit commands . . . . . . . . . . . . . . . . . . . . . . 180 table 10 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 table 11 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 12 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 13 intel bus interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 table 14 motorola bus interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 15 dma receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 table 16 dma transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 table 17 clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 table 18 ds3 transmit cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 19 ds3 receive cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 table 20 ds3 transmit overhead timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 21 ds3 receive overhead timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 22 ds3 transmit stuff timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 23 ds3 receive stuff bit timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 24 ds1/e1 transmit clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 25 ds1/e1 transmit data timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 table 26 ds1/e1 receive clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 27 ds1/e1 receive data timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 table 28 ds3 system clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 29 ds3 system transmit data timing . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 30 ds3 system receive data timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 204 table 31 jtag interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 table 32 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
peb 3445 e data sheet 12 2001-06-29
data sheet 13 2001-06-29 m13 multiplexer and ds3 framer TE3-MUX peb 3445 e v2.1 1 TE3-MUX overview the TE3-MUX integrates a ds3 framer, with a m13 multiplexer, a tributary interchanger/ line selector and 32 serial line interfaces for ds1/e1/j1 lines with 4:28 line protection capability. it is an economical solution for applications, which require ds3 framing but no ds1/e1 framers. this is often required in a central office where ds1/e1 from different equipment are multiplexed in a card. the TE3-MUX allows the ds1/e1 to be aggregated into ds3 without investing in the framers. line and remote loopback capabilities can be used to trouble shoot in case of broken connections and other failures. the use of standard line interfaces to interconnect office equipment is called office repeater bay (orb) compliance. 1.1 general features ? integrates a m13 multiplexer and a ds3 framer operating in m13 or c-bit parity mode ? optionally the m13 multiplexer can be disabled, which provides an integrated solution for combined channelized/unchannelized ds3 applications ? provides 32 tributary interfaces where each interface can be switched to any of the 28ds1/21e1 tributaries of the ds3 signal ? integrates a bit error rate tester ? integrates a 16-/8-bit switchable intel or motorola style microprocessor interface which operates in multiplexed or demultiplexed bus mode ? jtag boundary scan according to ieee1149.1 (5 pins). ? 0.25 m, 2.5v low power core technology ? i/os are 3.3v tolerant and have 3.3v driving capability ? package p-bga-272-1 (27mm x 27mm; pitch 1.27mm) ? full scan path and bist of on-chip rams for production test ? power consumption: 340mw (typical) ? temperature range -40..+85 c
peb 3445 e TE3-MUX overview data sheet 14 2001-06-29 1.1.1 m23 multiplexer and ds3 framer ? multiplexing/demultiplexing of seven ds2 into/from m13 asynchronous format according to ansi t1.107, ansi t1.107a ? multiplexing/demultiplexing of seven ds2 into/from c-bit parity format according to ansi t1.107, itu-t g.704 ? ds3 framing according to ansi t1.107, t1.107a, itu-t g.704 ? support of b3zs encoded signals ? provides access to the ds3 overhead bits and the ds3 stuffing bits via a serial clock and data interface (overhead interface) ? insertion and extraction of alarms according to ansi t1.404 (remote alarm, ais, far end receive failure) ? supports hdlc (path maintenance data link) and bit oriented message mode (far end alarm and control channel) in c-bit parity mode. an integrated signalling controller provides 2x32 byte deep fifo?s for each direction of both channels. ? detection of ais and idle signal in presence of ber 10 -3 ? detection of excessive zeroes and los ? alarm and performance monitoring with 16-bit counters for line code violations, excessive zeroes, parity error (p-bit), framing errors (f-bit errors with or without m-bit errors, far end block error (febe-bit) and cp-bit errors. ? automatic insertion of severely errored frame and ais defect indication 1.1.2 m12 multiplexer and ds2 framer ? multiplexing/demultiplexing of four asynchronous ds1 bit streams into/from m13 asynchronous format ? multiplexing/demultiplexing of 3 e1 signals into/from itu g.747 compliant ds2 signal. ? ds2 line loopback detection/generation ? framing according to ansi t1.107, t1.107a or itu-t g.747 ? insertion and extraction of x-bit ? insertion and extraction of alarms (remote alarm, ais) ? detection of ais in presence of ber 10 -3 ? alarm and performance monitoring (framing bit errors, parity errors) ? reframe time below 7ms (tr-tsy-000009) for ds2 format and below 1 ms for itu g.747 format ? bit stuffing/destuffing in m12 multiplex format or c-bit parity format ? insertion of ais in lieu of low speed tributaries 1.1.3 bit error rate tester ? user specified prbs or fixed pattern with programmable length of 2 to 32 bits and programmable feedback tap (prbs only) ? optional bit inversion ? two error insertion modes: single or programmable bit rates
peb 3445 e TE3-MUX overview data sheet 15 2001-06-29 ? optional zero suppression ? 32-bit counters for errors and received bits ? programmable bit intervals for receive measurements ? framed ds3, framed/unframed ds2 or framed/unframed ds1/e1 error insertion ? additional framing error counters for ds1/e1 error insertion
peb 3445 e TE3-MUX overview data sheet 16 2001-06-29 1.2 logic symbol ? figure 1 logic symbol TE3-MUX peb 3445 e jtag ttc(32:1) tovhck im lale dbw lint microprocessor interface rtc(32:1) rtd(32:1) ttd(32:1) tsbck tsbd tovhsyn tovhden tovhd rsbd rovhd rovhck rsbck rclk44 rd44n rd44p tclk44 td44n td44p rst rovhsyn la(7:0) ld(15:0) lrd/lds lwr/lrdwr lbhe/lble drr drt lcs trst tms tdo tdi tck scanen transmit line interface receive line interface transmit tributary interface receive tributary interface transmit overhead interface receive overhead interface tclko44 v ss v dd25 v dd3 rmc txme dma support ttc(1)
peb 3445 e TE3-MUX overview data sheet 17 2001-06-29 1.3 typical applications typical applications for the TE3-MUX support of channelized ds3 with serial line interfaces on the low speed side. the system partitioning due to orb compliance may allow usage in following systems: ? terminal multiplexers with ds1/e1 and hdsl interfaces ? add drop multiplexers (adm) with ds1/e1 and hdsl interfaces ? digital cross connect devices with ds1/e1 and hdsl interfaces ? dlc cot and rt ? channelized ds3 applications the TE3-MUX supports 32 low speed serial interfaces. these interfaces can be mapped to any of the 28 ds3 tributaries which provides for 4:28 protection. ? figure 2 typical ds3 channelized application te3-liu tm peb3452 TE3-MUX peb3445 quadliu tm #1 peb22504 quadliu tm #7 peb22504 ds3 digital ds1 #1 analog ds1 #28 analog ds1 digital ds3 analog
peb 3445 e pin description data sheet 18 2001-06-29 2 pin description 2.1 pin diagram (top view) figure 3 pin configuration rsbd tsbd tovhd rd44 rd44p td44n td44 td44p ld(14) tdo rovhsyn rovhd tovhsyn tovhck rd44n tclk44 ld(15) ld(13) trst tms tdi rsbck rovhck tovhden rclk44 tclko44 tck la(6) tsbck scanen la(5) la(7) la(4) la(3) la(0) la(2) lale la(1) lbhe lble lwr lrdwr lrd lds lcs dbw im drr drt lint txme rmc a b c d e f g h j k l m n p r t u v w y rst ld(12) ld(11) ld(0) ld(1) ld(2) ld(3) ld(4) ld(5) ld(6) ld(7) ld(8) ld(9) ld(10) rtc(32) rtc(10) rtc(20) rtc(1) rtc(11) rtc(21) rtc(2) rtc(12) rtc(22) rtc(3) rtc(23) rtc(4) rtc(24) rtc(5) rtc(6) rtc(25) rtc(7) rtc(8) rtc(9) rtc(13) rtc(14) rtc(15) rtc(16) rtc(17) rtc(18) rtc(19) rtc(26) rtc(27) rtc(28) rtc(29) rtc(30) rtc(31) rtd(32) rtd(10) rtd(20) rtd(1) rtd(11) rtd(21) rtd(2) rtd(12) rtd(22) rtd(3) rtd(23) rtd(4) rtd(24) rtd(5) rtd(6) rtd(25) rtd(7) rtd(8) rtd(9) rtd(13) rtd(14) rtd(15) rtd(16) rtd(17) rtd(18) rtd(19) rtd(26) rtd(27) rtd(28) rtd(29) rtd(30) rtd(31) ttc(32) ttc(10) ttc(20) ttc(1) ttc(11) ttc(21) ttc(2) ttc(12) ttc(22) ttc(3) ttc(23) ttc(4) ttc(24) ttc(5) ttc(6) ttc(25) ttc(7) ttc(8) ttc(9) ttc(13) ttc(14) ttc(15) ttc(16) ttc(17) ttc(18) ttc(19) ttc(26) ttc(27) ttc(28) ttc(29) ttc(30) ttc(31) ttd(32) ttd(10) ttd(20) ttd(1) ttd(11) ttd(21) ttd(2) ttd(12) ttd(22) ttd(3) ttd(23) ttd(4) ttd(24) ttd(5) ttd(6) ttd(25) ttd(7) ttd(8) ttd(9) ttd(13) ttd(14) ttd(15) ttd(16) ttd(17) ttd(18) ttd(19) ttd(26) ttd(27) ttd(28) ttd(29) ttd(30) ttd(31) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 nc1 nc20 nc19 nc18 nc17 nc16 nc15 nc14 nc13 nc12 nc11 nc10 nc9 nc8 nc7 nc6 nc5 nc4 nc3 nc2 nc23 nc22 nc21 vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vdd33 vdd33 vdd33 vdd33 vdd33 vdd33 vdd33 vdd33 vdd33 vdd33 vdd33 vdd33 vdd25 vdd25 TE3-MUX peb 3445 e
peb 3445 e pin description data sheet 19 2001-06-29 2.2 pin definitions and functions signal type definitions: i input is a standard input- only signal. o totem pole output is a standard active driver. i/o i/o is a bidirectional, tri-state input/output pin. o/d open drain allows multiple devices to share a line as a wire-or. a pull- up is required to sustain the inactive state until another agent drives it, and must be provided by the central resource. signal name conventions: ncn no-connect pin n such pins are not bonded with the silicon. although any potential at these pins will not impact the device it is recommended to leave them unconnected. no-connect pins might be used for additional functionality in later versions of the device. leaving them unconnected will guarantee hardware compatibility to later device versions. reserved reserved pins are for vendor specific use only and should be connected as recommended to guarantee normal operation. note: the signal type definition specifies the functional usage of a pin. this does not reflect necessarily the implementation of a pin, e.g. a pin defined of signal type ?input? may be implemented with a bidirectional pad.
peb 3445 e pin description data sheet 20 2001-06-29 2.3 local microprocessor interface ? pin no. symbol input (i) output (o) function d16 rst i reset j17 im i intel/motorola by connecting this pin to either v ss or v dd3 the bus interface can be adapted to either intel or motorola environment. im = v ss selects intel bus mode. im = v dd3 selects motorola bus mode. h20 dbw i data bus width dbw = v ss selects 8-bit bus mode. dbw = v dd3 selects 16-bit bus mode. e17, c20, d19, e18, e19, f18, g17, e20 la(7:0) i address bus these input address lines select one of the internal registers for read or write access. b11, a12, b12, c12, a13, b13, c13, a14, c14, a15, b15, d14, a16, b16, c16, a17 ld(15:0) i/o data bus bidirectional three-state data lines which interface with the system?s data bus. their configuration is controlled by the level of pin dbw: ? 8-bit mode (dbw = 0): ld(7:0) are active. ld(15:8) are in high impedance and have to be connected to v dd3 or v ss . ? 16-bit mode (dbw = 1): ld(15:0) are active. in case of byte transfers, the active half of the bus is determined by la(0) and lbhe /lble and the selected bus interface mode (im). the unused half is in high impedance. for detailed information, refer to chapter 5.1 . h19 lcs i chip select this active low signal selects the te3- mux for read/write operations.
peb 3445 e pin description data sheet 21 2001-06-29 f20 lale i address latch enable the address information provided on address lines la(7:0) is internally latched with the falling edge of lale. this function allows the TE3-MUX to be directly connected to a multiplexed address/data bus. in this case, pins la(7:0) must be externally connected to the data bus pins. when the TE3-MUX is operated in demultiplexed bus mode lale shall be connected to v dd3 . h18 lrd or lds i i read (intel bus mode) this active low signal selects a read transaction. data strobe (motorola bus mode) this active low signal indicates that valid data has to be placed on the data bus (read cycle) or that valid data has been placed on the data bus (write cycle). g20 lwr or lrdwr i i write enable (intel bus mode) this active low signal selects a write cycle. read write signal (motorola bus mode) this input signal distinguishes write from read operations. j20 lint od interrupt request this line indicates general interrupt requests of the TE3-MUX. the interrupt sources can be masked via registers. pin no. symbol input (i) output (o) function
peb 3445 e pin description data sheet 22 2001-06-29 g19 lbhe or lble i i byte high enable (intel bus mode) if 16-bit bus interface mode is enabled, this signal indicates a data transfer on the upper byte ld(15:8) of the data bus. in 8-bit bus interface mode this signal has no function and should be tied to v dd3 . refer to chapter 5.1 for detailed information. byte access (motorola bus mode) if 16-bit bus interface mode is enabled, this signal indicates a data transfer on the lower byte ld(7:0) of the data bus. in 8-bit bus interface mode this signal has no function and should be tied to v dd3 . refer to chapter 5.1 for detailed information. j18 drr o data request receive this signal indicates that the receive fifo of the path maintenance data link channel contains a byte which has to be read by an external cpu. k19 rmc o receive message complete this signal indicates that the dma controller has to read the port status register ppsr in order to release the receive fifo. j19 drt o data request transmit this signal indicates a request to store a new byte in the transmit fifo of the path maintenance data link channel. k18 txme i transmit message end this signal in combination with drt indicates that the byte written to the transmit fifo is the last byte of a hdlc message. txme has to asserted together with the data signal ld. pin no. symbol input (i) output (o) function
peb 3445 e pin description data sheet 23 2001-06-29 2.4 serial interface ? pin no. symbol input (i) output (o) function ds3 serial interface signals b10 tclk44 i ds3 transmit clock input this clock provides a reference clock for the ds3 interface. the frequency of this clock is nominally 44.736 mhz. c10 tclko44 o ds3 transmit clock output this output is a buffered version of the selected transmit clock. in normal operation mode tclko44 is a buffered version of tclk44. in looped timed mode tclko44 is a buffered version of rclk44. a11 td44 or td44p o o ds3 transmit data this unipolar serial data output represents the ds3 signal. td44 can be updated on the falling or the rising edge of tclko44. ds3 transmit positive pulse in dual-rail mode this pin represents the positive pulse of the b3zs encoded ds3 signal. td44p can be updated on the falling edge or rising edge of tclko44. a10 td44n o ds3 transmit negative pulse in dual-rail mode this pin represents the negative pulse of the b3zs encoded ds3 signal. td44n can be updated on the falling or rising edge of tclko44. c9 rclk44 i ds3 receive clock input this pin provides the receive clock input . the frequency of this clock is nominally 44.736 mhz.
peb 3445 e pin description data sheet 24 2001-06-29 a9 rd44 or rd44p i i ds3 receive data this unipolar serial data input represents the ds3 signal. rd44 can be sampled on the falling or rising edge of rclk44. ds3 receive positive pulse in dual-rail mode this pin represents the positive pulse of the b3zs encoded ds3 signal. rd44p can be sampled on the falling or rising edge of rclk44. b9 rd44n i ds3 receive negative pulse in dual-rail mode this pin represents the negative pulse of the b3zs encoded ds3 signal. rd44n can be sampled on the falling or rising edge of rclk44. ds3 overhead interface b5 tovhck o transmit overhead bit clock this signal provides the bit clock for the ds3 overhead bits of the outgoing ds3 frame. tovhck is nominally a 526 khz clock. a4 tovhd i transmit overhead data the overhead bits to be placed in the outgoing ds3 frame can be provided via tovhd. transmit overhead data is sampled on the rising edge of tovhck and those bits marked by tovhden are inserted in the overhead bit positions of the outgoing ds3 frame. c5 tovhden i transmit overhead data enable the asserted tovhden signal marks the bits to be inserted in the ds3 frame. tovhden is sampled together with tovhd on the rising edge of tovhd. pin no. symbol input (i) output (o) function
peb 3445 e pin description data sheet 25 2001-06-29 b4 tovhsyn i/o transmit overhead synchronization tovhsyn provides the means to align tovhd to the first m-frame of the ds3 signal or to align the first m-frame to tovhsyn . ? if operated in output mode tovhsyn is asserted when the x-bit of the 1 st subframe of the ds3 multiframe has to be inserted via tovhd. tovhsyn is updated on the falling edge of tovhck. ? if operated in input mode tovhsyn must be asserted when the x-bit of the 1 st m-frame of the ds3 signal is output on td44. tovhsyn is sampled on the rising edge of tclko44. d5 tsbck o transmit stuff bit clock this signal provides the bit clock for ds3 transmit stuff bit data. a3 tsbd i transmit stuff bit data data provided via tsbd is optionally inserted in the stuffed bit positions of the ds3 signal. tsbd is sampled on the rising edge of tsbck. this function is available in m13 asynchronous format only. c4 rovhck o receive overhead bit clock this signal provides the bit clock for the received ds3 overhead bits. rovhck is nominally a 526 khz clock. b3 rovhd o receive overhead data rovhd contains the extracted overhead bits of the ds3 frame. it is updated on the falling edge of rovhck. pin no. symbol input (i) output (o) function
peb 3445 e pin description data sheet 26 2001-06-29 b2 rovhsyn o receive overhead synchronization rovhsyn is asserted while the x-bit of the 1 st subframe of the ds3 signal is provided via rovhd. it is updated on the falling edge of rovhck. c3 rsbck o receive stuff bit clock this signal provides the bit clock for ds3 receive stuff bit data. a2 rsbd o receive stuff bit data rovhd provides data which was inserted in the stuffed bit positions of the ds3 signal. rsbd is updated on the falling edge of rsbck. this function is available in m13 asynchronous format only. ds1/e1 interface signals, ds3 system interface signals l20, m19, n18, r20, t20, t17, w20, w18, v16, u14, y15, y13, y12, y11, w9, w8, v7, y5, y3, y2, t4, u1, t1, p1, m4, l4, k3, j3, h3, f2, e2, e4 e4 rtc(32:1) or rtc(1) o o ds1/e1 receive clock this interface provides the receive clock for each of the low speed interfaces. dependent on the tributary (ds1/e1) this clock has a nominal frequency of 1.544 mhz or 2.048 mhz. due to the destuffing and demultiplexing process the receive clock contains gaps. ds3 receive clock when the TE3-MUX is operated in unchannelized mode (ds3 framer mode) this interface provides the ds3 receive payload clock. it is derived from the receive clock rclk44 and has clock gaps on the ds3 bit positions containing the overhead bits. pin no. symbol input (i) output (o) function
peb 3445 e pin description data sheet 27 2001-06-29 k20, m20, n19, p18, r18, v20, v19, y19, w17, v15, v14, w13, w12, w11, y9, y8, w7, v6, y4, w4, u3, t3, p4, p2, n1, m1, k1, j2, h2, f1, e1, c1 c1 rtd(32:1) or rtd(1) o o ds1/e1 receive data the data stream of the ds1/e1 tributary is directly feeded to this output. rtd(x) is updated on the rising or falling edge of rtc(x). ds3 receive data when the TE3-MUX is operated in unchannelized mode (ds3 framer mode) the payload of the incoming ds3 signal is output on rtd(1). rtd(1) is updated on the falling edge of rtc(1). pin no. symbol input (i) output (o) function
peb 3445 e pin description data sheet 28 2001-06-29 l19, m17, p19 , p17, t18, u19, v18, u16, w16, w15, y14, v12, v11, v10, u9, y7, w6, v5, v4, w1, u2, r3, p3, n2, m2, l2, j1, h1, g2, f3, d1, d2 d2 ttc(32:1) or ttc(1) i o ds1/e1 transmit clock transmit data is sampled on the rising edge of ttc(x) and inserted into the assigned ds1/e1 tributary of the ds3 signal. dependent on the tributary type ttc(x) has a clock frequency of 1.544 mhz or 2.048 mhz. ds3 transmit clock when the TE3-MUX is operated in unchannelized mode (ds3 framer mode) this interface provides the ds3 transmit payload clock. it is derived from the transmit clock tclko44 and has clock gaps on the ds3 bit positions containing the overhead bits. l18, m18, p20, r19, t19, u18, w19, v17, y17, y16, w14, u12, u11, y10, v9, v8, y6, w5, u5, w3, v1, t2, r2, n3, m3, l3, k2, j4, g1, g4, e3, d3 d3 ttd(32:1) or ttd(1) i i ds1/e1 transmit data ttd(x) provides the ds1/e1 data stream to be inserted in the assigned ds1/e1 tributary of the ds3 signal. ttd(x) can be sampled on the rising or falling edge of ttc(x). ds3 transmit data when the TE3-MUX is operated in unchannelized mode (ds3 framer mode) the payload of the outgoing ds3 signal needs to be provided via ttd(1). ttd(1) is sampled on the rising edge of ttc(1) pin no. symbol input (i) output (o) function
peb 3445 e pin description data sheet 29 2001-06-29 2.5 test interface ? pin no. symbol input (i) output (o) function c17 tck i jtag test clock this pin is connected with an internal pull- up resistor. b18 tms i jtag test mode select this pin is connected with an internal pull- up resistor. b19 tdi i jtag test data input this pin is connected with an internal pull- up resistor. a19 tdo o jtag test data output b17 trst i jtag test reset this pin is connected with an internal pull- up resistor. d7 scanen i full scan path test enable when connected to v dd3 the TE3-MUX works in a vendor specific test mode. it is recommended to connect this pin to v ss .
peb 3445 e pin description data sheet 30 2001-06-29 2.6 power supply, reserved pins and no-connect pins ? pin no. symbol input (i) output (o) function a1, d4, d8, d13, d17, h4, h17, n4, n17, u4, u8, u13, u17, j9, j10, j11, j12, k9, k10, k11, k12, l9, l10, l11, l12, m9, m10, m11, m12 v ss i ground 0v all pins must have the same level. a18, b14, c2, c6, c11, d9, d18, g3, g18, k17, l1, n20, r1, u7, u20, v13, v2, w10, y18 v dd25 i supply voltage 2.5v 0.25v all pins must have the same level. d6, d11, d15, f4, f17, k4, l17, r4, r17, u6, u10, u15 v dd3 i supply voltage 3.3v 0.3v all pins must have the same level. a5, a6, a7, a8, a20, b1, b6, b7, b8, b20, c7, c8, c15, c18, c19, d10, d12, d20, f19, v3, w2, y1, y20 nc1..23 no-connect pins 1..23 it is recommended not to connect these pins.
peb 3445 e general overview data sheet 31 2001-06-29 3 general overview 3.1 block diagram ? figure 4 block diagram dbw local loop m12 demux ds2 transmit framer m12 mux unipolar/ bipolar encoding unipolar/ bipolar decoding ds3 transmit framer ds3 receive framer tc44o tc44 rd44n rd44p rc44 td44n td44p ds2 transmit framer ds2 transmit framer m23 mux m12 mux m12 demux m23 demux signalling controller (feac/path maintenance data link) microprocessor interface 8/16-bit intel/motorola 1 7 1 7 tributary interface tributary interface rtd(32:1) rtc(32:1) receive overhead access transmit overhead access 1 7 1 7 im lale la(7:0) ld(15:0) local/remote loop remote loop 1 7 4 4 remote loop 4 4 ttd(32:1) ttc(32:1) local loop 1 7 4 32 32 tovhck tsbck tsbd tovhden tovhd rsbd rovhd rovhck rsbck jtag tms tdo tdi tck v ss v dd25 v dd3 rst scanen reset scanlogic tovhsyn rovhsyn drr rmc drt txme lcs lwr/lrdwr lrd/lds lbhe/lble lint trst ttc(1)
peb 3445 e general overview data sheet 32 2001-06-29 3.2 block description 32 port line selector/tributary mapper this structure allows the user to connect any ds1/e1 signal to a specified tributary of any m12 module. therefore it maps 32 ds1/e1 signals into 28 ds1 time slots or 21 e1 time slots of the ds3 signal. the four remaining spare ports can be used for microcontroller based protection, e.g. they can be operated in stand-by mode. they can also be used to interface an external test unit to test any ds1/e1. m12 multiplexer/demultiplexer and ds2 framer there are seven independent m12 multiplexer/demultiplexer modules in the chip. each module can operate in either ansi t1.107, ansi t1.107a or itu-t g.747 mode. in other words, a module can either map 4 ds1/j1 to one ds2 or 3 e1 to one ds2. when mapping ds1 signals into ds2 signals the m12 multiplexer performs inversion of the second and fourth ds1 signal. the ds2 framer performs frame and multi-frame alignment in receive direction and vice versa inserts the framing bits according to ansi t1.107, ansi t1.107a or itu-t g.747. it detects loopback requests or enables insertion of loopback requests under microprocessor control. m23 multiplexer/demultiplexer and ds3 framer in channelized operating mode the m23 multiplexer/demultiplexer maps/demaps seven ds2 signals (generated by the m12 multiplexer/demultiplexer and ds2 framer) into/from m13 asynchronous format or c-bit parity format. in unchannelized mode one logical input stream is mapped into the information bits of the ds3 stream according to ansi t1.107, ansi t1.107a. the ds3 framer performs frame and multiframe alignment in receive direction and inserts the frame and multiframe alignment bits. access to the ds3 overhead bits is provided by an additional overhead interface or via internal registers. an integrated signalling controller supports the far end alarm and control channel and the c-bit parity path maintenance data link in dma or interrupt mode. performance monitoring provides counting of framing bit errors, parity errors, cp-bit errors, far end block errors, excessive zeros and line code violations. the framer detects loopback requests and allows insertion of loopbacks under microprocessor control. bert/prbs generator/detector the device has an integrated bit error rate tester. it is a programmable pseudo random bit sequence generator/monitor capable of supporting any smart jack loopback code from 2 to 32 bits in length and with a programmable feedback tap. the monitor can detect the incoming pattern and transmit the same pattern towards the far end of any low speed/ high speed port.
peb 3445 e general overview data sheet 33 2001-06-29 the test unit also has single/multi bit error insertion for testing and diagnostics and supports framed ds3, framed/unframed ds2 and framed/unframed ds1/e1 error insertion.
peb 3445 e functional description data sheet 34 2001-06-29 4 functional description 4.1 remote and local loops 4.1.1 local loops local loops are provided on ds3 and ds1 level on a per port/tributary basis. in the local loop the outgoing bit stream of a port/tributary is mirrored to the receive data path. this allows to provide data via the low speed tributaries which is processed by the TE3-MUX in transmit direction, mirrored to the respective receiver and send back to the originating source. in order to ensure that the local port loop works even without incoming receive clock, each line looped uses the corresponding transmit clock. ? figure 5 local loops 4.1.2 remote loops the TE3-MUX supports remote loops in different stages of the m13 data path. in ds3 line loopback mode the incoming ds3 signal is mirrored and placed on the ds3 signal output. while operating in ds3 line loopback mode, the incoming receive clock rclk44 is used to update outgoing transmit data. in ds2 line loopback mode one or more ds2 receive framer ds1/e1 interface m12 demux ds2 transmit framer m12 multiplexer ds1/e1 interface ds3 receive framer m23 demux m23 multiplexer ds3 transmit framer rd44p rclk44 rd44n td44p tclko44 td44n tclk44 ds2 receive framer ds1/e1 interface m12 demux ds2 transmit framer m12 multiplexer ds1/e1 interface ds3 receive framer m23 demux m23 multiplexer ds3 transmit framer rd44p rclk44 rd44n td44p tclko44 td44n tclk44
peb 3445 e functional description data sheet 35 2001-06-29 selectable ds2 signals are looped after the m23 stage the of the TE3-MUX. finally the ds1/e1 line loopback mode mirrors one or more incoming lines. tributary data provided via the low speed serial interface is replaced by the mirrored data stream. ? figure 6 remote loops ds3 receive framer m23 demux m23 multiplexer ds2 receive framer ds3 transmit framer rd44p rclk44 ds1/e1 interface rd44n td44p tclko44 td44n m12 demux ds2 transmit framer m12 multiplexer ds1/e1 interface ds3 receive framer m23 demux m23 multiplexer ds2 receive framer ds3 transmit framer ds1/e1 interface m12 demux ds2 transmit framer m12 multiplexer ds1/e1 interface ds3 receive framer m23 demux m23 multiplexer ds2 receive framer ds1/e1 interface m12 demux ds2 transmit framer m12 multiplexer ds1/e1 interface rd44p rclk44 rd44n rd44p rclk44 rd44n tclk44 td44p tclko44 td44n tclk44 ds3 transmit framer td44p tclko44 td44n tclk44
peb 3445 e functional description data sheet 36 2001-06-29 4.2 b3zs code in the b3zs line code each block of three consecutive zeros is replaced by either of two replacements codes which are b0v and 00v, where b represents a pulse which applies to the bipolar rule (?+1? or ?-1?) and v represents a bipolar violation (two consecutive ?+1? or ?-1? bits). the replacement code is chosen in a way that there is an odd number of valid b pulses between consecutive v pulses to avoid the introduction of a dc component into the analog signal. the receive line decoder decodes the incoming b3zs dual rail data signal and changes the replacement patterns to the original three-zeros pattern. pattern sequences violating these rules are reported as bipolar violation errors.
peb 3445 e functional description data sheet 37 2001-06-29 4.3 tributary mapper the tributary mapper connects any of the 28 low speed tributaries to any of the 32 ds1/ e1 low speed interfaces. a ds3 tributary consists of seven ds2 tributaries. each ds2 tributaries consists of four ds1 tributaries when operated in ds1 format or three e1 tributaries when operated in itu-t g.747 format. when a ds2 tributary is operated in itu-t g.747 format the first three tributaries of a m12 multiplexer are accessible only. the fourth tributary of that m12 multiplexer is not used. mapping of the tributaries to the serial interfaces can be done independently in receive and transmit direction. after reset the tributary mapper maps the tributaries 1..28 to the port interfaces 1..28 and the spare lines 29..32 to the port interfaces 29..32. ? figure 7 tributary mapper 5 6 7 8 1 2 3 4 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 5 6 7 8 1 2 3 4 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 m23 multiplexer stage m12 multiplexer stage switching stage tributaries marked with shade are not accessible if tributary is operated in itu-t g.747 mode tributary # interface # ds3 interface 29 30 31 32
peb 3445 e functional description data sheet 38 2001-06-29 transmit path figure 8 shows the ds1/e1 transmit part of the TE3-MUX. each m12 multiplexer is assigned one input switch which maps 4 out of 32 input signals to the four inputs of the m12 multiplexer. the multiplexer as well as the switch to be programmed are selected via d2tsel.gn. then the four outputs of the switch are configured using register d2ttm0..3. additionally each line can be switched into remote loop mode or one selected line can be fed via the integrated bit error rate tester. ? figure 8 tributary mapper (transmit direction) receive path in receive direction a group of four consecutive output ports is assigned to one output switch (see figure 9 ). this output switch maps any of the 28 m12 demultiplexer outputs or any of the four internal spare links to its four outputs. the output multiplexer to be programmed is selected via d2rsel.gn. then the four outputs of the switch are programmed via d2rtm0..3. #0 ttc(1) ttd(1) m12 mux #0 #6 m12 mux #6 #7 ttc(32) ttd(32) to m23 stage + + from receive path or test unit 32 32 32 0 1 2 3 0 1 2 3 spare links 0 1 2 3 0 1 2 3 0 1 2 3 to receive path
peb 3445 e functional description data sheet 39 2001-06-29 ? figure 9 tributary mapper (receive direction) #0 rtc(1) rtd(1) m12 demux #0 m12 demux #6 #7 rtc(32) rtd(32) from m23 stage 0 1 2 3 0 1 2 3 spare links + + 0 1 2 3 0 1 2 3 32 32 from transmit path to transmit path
peb 3445 e functional description data sheet 40 2001-06-29 4.4 m12 multiplexer/demultiplexer and ds2 framer the m12 multiplexer and the ds2 framer can be operated in two modes: ? m12 multiplex format according to ansi t1.107 ? itu-t g.747 format 4.4.1 m12 multiplex format the framing structure of the m12 signal is shown in table 1 . a ds2 multiframe consists of four subframes. each subframe combines 6 blocks with 49 bits each. the first bit of each block contains an overhead (oh) bit and 48 information bits. the 48 information bits are formed by bit-by-bit interleaving of the four ds1 signals or a total of 12 bits from each ds1 signal. the first bit is assigned to the 1 st tributary ds1 signal, the second bit is assigned to the 2 nd tributary ds1 signal and so on. table 1 m12 multiplex format m 0 , m 1 m 0 and m 1 form the multiframe alignment signal. each ds2 multiframe consists of three m-bits and they are located in bit 0 of subframe one through three. the multiframe alignment signal is ?011?. x this bit is the fourth bit of the multiframe alignment signal and can be set to either ?0? or ?1?. it is accessible via an internal register. f 0 , f 1 f 0 and f 1 form the frame alignment pattern. each ds2 multiframe consists of eight f-bits, two per subframe in block 3 and 6. f 0 and f 1 form the pattern ?01?. this pattern is repeated in every subframe. c 11 ..c 43 the c-bits control the bit stuffing procedure of the multiplexed ds1 signals. [48] these bits represent a data block, which consists of 48 bits. [48] consists of four time slots of 12 bit and each time slot is assigned to one of four participating ds1 signals. subframe block 1 through 6 of a subframe 123456 ds2- multiframe 1m 0 [48] c 11 [48] f 0 [48] c 12 [48] c 13 [48] f 1 [48] 2m 1 [48] c 21 [48] f 0 [48] c 22 [48] c 23 [48] f 1 [48] 3m 1 [48] c 31 [48] f 0 [48] c 32 [48] c 33 [48] f 1 [48] 4x[48]c 41 [48] f 0 [48] c 42 [48] c 43 [48] f 1 [48]
peb 3445 e functional description data sheet 41 2001-06-29 4.4.1.1 synchronization procedure the integrated ds2 framer searches for the frame alignment pattern ?01? and the multiframe alignment pattern in each of the seven ds2 frames which are contained in a ds3 signal. frame alignment is declared, when the ds2 framer has found the basic frame alignment pattern (f-bit) and the multiframe alignment pattern (m-bit). loss of frame is declared, when 2 out of 4 or 3 out of 5 incorrect f-bits are found or when one or more incorrect m-bits are found in 3 out of 4 subframes. 4.4.1.2 multiplexer/demultiplexer demultiplexer the demultiplexer extracts four ds1 signals out of each ds2 signal. if two out of three bits of c i1 , c i2 , c i3 are set to ?1? the first information bit in the i th subframe and the 6 th block which is assigned to the i th ds1 signal is discarded. the demultiplexer performs inversion of the 2 nd and 4 th tributary ds1 signal. multiplexer the multiplexer combines four ds1 signals to form a ds2 signal. stuffing bits are inserted and the c i1 -, c i2 -, c i3 -bits, which are assigned to the i th ds1 signal, are set to ?1? in case that not enough data is available. the 2 nd and 4 th ds1 signal are automatically inverted in transmit direction. 4.4.1.3 loopback control detection loopback requests encoded in the c-bits of the ds2 signal are flagged when they are repeated for at least five ds2 multiframes. loops must be initiated by an external microprocessor. generation a loopback request, which is transmitted in lieu of the c-bits, can be placed in each ds2 signal.
peb 3445 e functional description data sheet 42 2001-06-29 4.4.1.4 alarm indication signal detection ais is declared, when the ais condition (the received ds2 data stream contains an all ?1? signal with less then 3/9 zeros within 3156 bits while the ds2 framer is out of frame) is present within a time interval that is determined by register d2rap. generation the alarm indication signal is an all ?1? unframed signal and will be transmitted if enabled.
peb 3445 e functional description data sheet 43 2001-06-29 4.4.2 itu-t g.747 format the multiplexing frame structure is shown in table 2 . table 2 itu-t g.747 format 4.4.2.1 synchronization procedure the integrated framer searches for the frame alignment pattern ?111010000? in each of the seven ds2 frames which are contained in a ds3 signal. frame alignment is declared, when the framer has found three consecutive correct frame alignment signals. if the frame alignment signal has been received incorrectly in one of the following frames after the receiver found the first correct frame alignment signal a new frame search is started. loss of frame is declared, when four consecutive frame alignment signals have been received incorrectly. 4.4.2.2 multiplexer/demultiplexer demultiplexer the demultiplexer extracts three e1 signals from each 6.312 mhz signal. if two out of three bits of c j1 , c j2 , c j3 are set to ?1? the available justification bit of the j th e1 signal is discarded. set content bit itu-t g.747 frame i frame alignment signal 111010000 1 to 9 bits from tributaries 10 to 168 ii alarm indication to the remote multiplex equipment 1 parity bit 2 reserved 3 bits from tributaries 4 to 168 iii justification control bits c j1 1 to 3 bits from tributaries 4 to 168 iv justification control bits c j2 1 to 3 bits from tributaries 4 to 168 v justification control bits c j3 1 to 3 bits from tributaries available for justification 4 to 6 bits from tributaries 7 to 168
peb 3445 e functional description data sheet 44 2001-06-29 multiplexer the multiplexer combines three e1 signals to form a ds2 signal. stuffing bits are inserted and the c j1 -, c j2 -, c ij -bits, which are assigned to the j th e1 signal, are set to ?1? in case that not enough data is available. 4.4.2.3 parity bit detection the receiver optionally calculates the parity of all tributary bits and compares this value with the received parity bit. differences are counted in the parity error counter. generation the parity bit is automatically calculated according to itu-t g.747 or programmable to a fixed value under microprocessor control. 4.4.2.4 remote alarm indication detection remote alarm is reported when bit 1 of ?set ii? (see table 2 "itu-t g.747 format" on page 43 ) changes and when the change persists for at least three multiframes. generation remote alarm is transmitted in bit 2 of ?set ii? and can be inserted under microprocessor control. 4.4.2.5 alarm indication signal detection ais is declared, when the ais condition (the received ds2 data stream contains an all ?1? signal with less then 5/9 zeros within two consecutive multiframes while the ds2 framer is out of frame) is present within a time interval that is determined by register d2rap. generation the alarm indication signal is an all ?1? unframed signal and will be transmitted if enabled.
peb 3445 e functional description data sheet 45 2001-06-29 4.5 m23 multiplexer and ds3 framer the ds3 path of the TE3-MUX can be operated in three modes: ? m23 multiplex format ? c-bit parity format with modified m23 multiplex operation ? full payload rate format 4.5.1 m23 multiplex format the framing structure of the m23 multiplex signal is shown in table 3 . each ds3 multiframe consists of 7 subframes and each subframe of eight blocks. one block consists of 85 bits, where the first bit is the overhead (oh) bit and the remaining 84 bits contain the information bits. the 84 information bits are formed by bit-by-bit interleaving of the seven ds2 signals or a total of 12 bits from each ds2 signal. the first bit is assigned to the 1 st tributary ds2 signal, the second bit is assigned to the 2 nd tributary ds2 signal and so on. table 3 m23 multiplex format f 0 , f 1 f 0 and f 1 form the frame alignment pattern. each ds3 frame consists of 28 f-bits, four per subframe in block 2, 4, 6 and 8. f 0 and f 1 form the pattern ?1001?. this pattern is repeated in every subframe. m 0 , m 1 m 0 and m 1 form the multiframe alignment signal. the m-bit is contained in the oh-bit of the first block in subframe 5,6 and 7. the multiframe alignment signal is ?010?. c 11 ..c 73 the c-bits control the bit stuffing procedure of the multiplexed ds2 signals. p the p-bits contain parity information and are calculated as even parity on all information bits of the previous ds3 frame. both p-bits are identical. sub- frame block 1 through 8 of a subframe 12345678 ds3- multi- frame 1x[84]f 1 [84] c 11 [84] f 0 [84] c 12 [84] f 0 [84] c 13 [84] f 1 [84] 2x[84]f 1 [84] c 21 [84] f 0 [84] c 22 [84] f 0 [84] c 23 [84] f 1 [84] 3p[84]f 1 [84] c 31 [84] f 0 [84] c 32 [84] f 0 [84] c 33 [84] f 1 [84] 4p[84]f 1 [84] c 41 [84] f 0 [84] c 42 [84] f 0 [84] c 43 [84] f 1 [84] 5m 0 [84] f 1 [84] c 51 [84] f 0 [84] c 52 [84] f 0 [84] c 53 [84] f 1 [84] 6m 1 [84] f 1 [84] c 61 [84] f 0 [84] c 62 [84] f 0 [84] c 63 [84] f 1 [84] 7m 0 [84] f 1 [84] c 71 [84] f 0 [84] c 72 [84] f 0 [84] c 73 [84] f 1 [84]
peb 3445 e functional description data sheet 46 2001-06-29 x the x-bits are used for transmission of asynchronous in-service messages. both x-bits must be identical and may not change more than once every second. [84] these bits represent a data block, which consists of 84 bits. [84] consists of seven time slots with 12 bits each and they are assigned to one of the seven participating ds2 signals. 4.5.1.1 synchronization procedure the integrated ds3 framer searches for the frame alignment pattern ?1001? and when found for the multiframe alignment pattern in each of the seven ds3 subframes. when the multiframe alignment pattern is found in three consecutive ds3 frames while frame alignment is still valid frame alignment is declared. the p-bits and the x-bits are ignored during synchronization. loss of frame is declared, when 3 out of 8 or 3 out of 16 incorrect f-bits are found or when one or more incorrect m-bits are found in 3 out of 4 subframes. 4.5.1.2 multiplexer/demultiplexer demultiplexer the demultiplexer extracts seven ds2 signals from the incoming ds3 signal. if two or three bits out of c i1 , c i2 , c i3 are set to ?1? the first bit following the f 1 bit in the i th subframe which is assigned to the i th ds2 signal is discarded. multiplexer the multiplexer combines seven ds2 signals to form a ds3 signal. if not sufficient data is available for a ds2 signal, it automatically inserts a stuffing bit and sets the bits c i1 , c i2 , c i3 assigned to the i th ds2 signal to ?1?. 4.5.1.3 x-bit the TE3-MUX provides access to the x-bit via an internal register. data written to the x- bit register is copied to an internal shadow register which is then locked for one second after each write access.
peb 3445 e functional description data sheet 47 2001-06-29 4.5.1.4 alarm indication signal, idle signal detection alarm indication signal or idle signal is declared, when the selected signal format was received with less than 8/15 bit errors (selectable via bit d3rap.ais) for at least one multiframe. the alarm indication signal can be selected as: ? unframed all ?1?s ? framed ?1010? sequence, starting with a binary ?1? after each oh-bit. c-bits are set to ?0?. x-bit can be checked as ?1? or x-bit check can be disabled. the idle signal is a ? framed ?1100? sequence, starting with a binary ?11? after each oh-bit. c-bits are set to ?0? in m-subframe 3. x-bit can be checked as ?1? or x-bit check can be disabled. generation the alarm indication signal or idle signal will be generated according to the selected signal format. x-bit needs to be set separately to ?1?. 4.5.1.5 loss of signal detection loss of signal is declared, when the incoming data stream contains more than 175 consecutive ?0?s. recovery loss of signal is removed, when two or more ones are detected in the incoming data stream. 4.5.1.6 performance monitor the following conditions are counted: ? line code violations ? excessive zeroes ? p-bit errors, cp-bit errors ? framing bit errors ? multiframe bit errors ? far end block errors
peb 3445 e functional description data sheet 48 2001-06-29 4.5.2 c-bit parity format the framing structure of the c-bit parity format is shown in table 3 . the assignment of the information bits [84] is identical to the m23 multiplex format, but the function of the c-bits is redefined for path maintenance and data link channels. table 4 c-bit parity format f 0 , f 1 f 0 and f 1 form the frame alignment pattern. each ds3 frame consists of 28 f-bits, four per subframe in block 2, 4, 6 and 8. f 0 and f 1 form the pattern ?1001?. this pattern is repeated in every subframe. m 0 , m 1 m 0 and m 1 form the multiframe alignment signal. the m-bit is contained in the oh-bit of the first block in subframe 5,6 and 7. the multiframe alignment signal is ?010?. n r reserved. set to ?1? in transmit direction. aic application identification channel. dl t the terminal-to-terminal path maintenance data link uses the hdlc protocol. access to the dl t bits is possible via the integrated signalling controller. dl reserved. access to the dl-bits is possible via the spare bit registers. feac the alarm or status information of a far end terminal is sent back over the far end and control channel. this bit also contains ds3 or ds1 line loopback requests. messages are sent in bit oriented mode. the far end alarm and control channel can be accessed via the internal signalling controller. sub- frame block 1 through 8 of a subframe 12345678 ds3- multi- frame 1x[84]f 1 [84] aic [84] f 0 [84] n r [84] f 0 [84] feac [84] f 1 [84] 2x[84]f 1 [84] dl [84] f 0 [84] dl [84] f 0 [84] dl [84] f 1 [84] 3p[84]f 1 [84] cp [84] f 0 [84] cp [84] f 0 [84] cp [84] f 1 [84] 4p[84]f 1 [84] febe [84] f 0 [84] febe [84] f 0 [84] febe [84] f 1 [84] 5m 0 [84] f 1 [84] dl t [84] f 0 [84] dl t [84] f 0 [84] dl t [84] f 1 [84] 6m 1 [84] f 1 [84] dl [84] f 0 [84] dl [84] f 0 [84] dl [84] f 1 [84] 7m 0 [84] f 1 [84] dl [84] f 0 [84] dl [84] f 0 [84] dl [84] f 1 [84]
peb 3445 e functional description data sheet 49 2001-06-29 febe the far end block error bits indicate a cp-bit parity error or a framing error. they are used to monitor the performance of a ds3 signal. upon detection of either error in the incoming data stream the febe-bits are set automatically to ?000? in the outgoing direction. received far end block errors are counted. cp the cp-bits are used to carry path parity information and are set to the same value as the p-bits. in receive direction the cp-bits are checked against the calculated parity and differences are counted. p the p-bits contain parity information and are automatically calculated as even parity on all information bits of the previous ds3 frame. x the x-bits are used for transmission of asynchronous in-service messages. both x-bits must be identical and may not change more than once every second. access to the x-bits is possible via a register. [84] these bits represent a data block, which consists of 84 bits. [84] consists of seven time slots with 12 bits each and they are assigned to one of the seven participating ds2 signals. 4.5.2.1 synchronization procedure the integrated ds3 framer searches for the frame alignment pattern ?1001? and when found for the multiframe alignment pattern in each of the seven ds3 subframes. frame alignment is declared when the multiframe alignment pattern is found in three consecutive ds3 frames. the p-bits and the x-bits are ignored during synchronization. loss of frame is declared, when 3 out of 8 or 3 out of 16 incorrect f-bits are found or when one or more incorrect m-bits are found in 3 out of 4 subframes. 4.5.2.2 multiplexer/demultiplexer demultiplexer the demultiplexer extracts seven ds2 signals from the incoming ds3 signal. since the ds3 signal is always stuffed the stuffing bit assigned to each ds2 signal is discarded. multiplexer the multiplexer combines seven ds2 signals to form a ds3 signal and automatically inserts a stuffing bit for each ds2 signal. 4.5.2.3 x-bit the TE3-MUX provides access to the x-bits via internal registers.
peb 3445 e functional description data sheet 50 2001-06-29 4.5.2.4 far end alarm and control channel the far end alarm and control channel is handled via an internal bom controller (see chapter 4.6, signalling controller). the following byte format is assumed (the left most bit is received first): 111111110xxxxxx0 b the far end alarm and control channel uses the ff h byte for synchronization. message words start and end with a ?0?. 4.5.2.5 loopback control detection loopback requests are encoded in the messages of the far end alarm and control channel. the microprocessor has access to the messages as described in chapter 4.5.2.4 . generation a loopback request can be initiated via the far end alarm and control channel. 4.5.2.6 alarm indication signal, idle signal detection alarm indication signal or idle signal is declared, when the selected signal format was received with less than 8/15 bit errors (selectable via bit d3rap.ais) for at least one multiframe. the alarm indication signal can be selected as: ? unframed all ?1?s ? framed ?1010? sequence, starting with a binary ?1? after each oh-bit. c-bits are set to ?0?. x-bit can be checked as ?1? or x-bit check can be disabled. the idle signal is a ? framed ?1100? sequence, starting with a binary ?11? after each oh-bit. c-bits are set to ?0? in m-subframe 3. x-bit can be checked as ?1? or x-bit check can be disabled. generation the alarm indication signal or idle signal will be generated according to the selected signal format. x-bit needs to be set separately to ?1?.
peb 3445 e functional description data sheet 51 2001-06-29 4.5.2.7 loss of signal detection loss of signal is declared, when the incoming data stream contains more than 175 consecutive ?0?s. recovery loss of signal is removed, when two or more ones are detected in the incoming data stream. 4.5.2.8 performance monitor the following conditions are counted: ? line code violations ? excessive zeroes ? p-bit errors, cp-bit errors ? framing bit errors ? multiframe bit errors ? far end block errors
peb 3445 e functional description data sheet 52 2001-06-29 4.5.3 full payload rate format in full payload rate format the ds3 multiframe structure can be selected according to m13 multiplex structure or c-bit parity structure. in either case the data blocks [84] carry one continuous data stream which is provided via the tributary interface one. multiplexing/demultiplexing of the data block [84] does not apply.
peb 3445 e functional description data sheet 53 2001-06-29 4.6 signalling controller the signalling controller provides access to the far end alarm and control channel and to the c-bit parity path maintenance data link channel. note: the c-bit parity path maintenance data link channel and the far end alarm and control channel support the same register structure. registers assigned to the c- bit parity path maintenance data link channel start with a ?p?, registers assigned to the far end alarm and control channel start with a ?f?. 4.6.1 c-bit parity path maintenance data link channel the TE3-MUX performs the flag generation, crc generation, zero bit-stuffing and programmable idle code generation. buffering of transmit/receive data is done in 2x32 byte deep fifos. the TE3-MUX additionally supports dma support signals for operation of the c-bit parity path maintenance data link channel. shared flags the closing flag of a previously transmitted frame simultaneously becomes the opening flag of the following frame if there is one to be transmitted. the shared flag feature is enabled by setting pxcr.sf. crc check as an option in hdlc mode the internal handling of received and transmitted crc checksum can be influenced via control bits prcfg.crcdis and pxcfg.discrc. ? receive direction the received crc checksum is always assumed to be in the last two bytes of a frame, immediately preceding a closing flag. if prcfg.crcdis is set, the received crc checksum will be written to the receive fifo where it precedes the frame status byte. the received crc checksum is additionally checked for correctness. ? transmit direction if pxcfg.discrc is set, the crc checksum is not generated internally. the checksum has to be provided via the transmit fifo (pxff.xfifo) as the last two bytes. the transmitted frame will only be closed automatically with a (closing) flag. 4.6.2 far end alarm and control channel (bom) the bom controller supports the far end alarm and control channel according to ansi t1.404.
peb 3445 e functional description data sheet 54 2001-06-29 data transmission transmission of bom data is done by using a transparent mode of the signalling controller. after having written 1 to 32 bytes to the transmit fifo, the command ?start transmission, enable automatic repetition? via the handshake register fhnd forces the TE3-MUX to repeatedly transmit the data stored in the transmit fifo to the remote end. the cyclic transmission continues until a reset command (fhnd.xres) is issued or until the command ?stop transmission, disable automatic repetition? is written to the handshake register fhnd. afterwards an all ?1? pattern is transmitted. the transmitter does not insert ff h itself. data stored in the transmit fifo has to include the ff h byte as well and has to follow the following byte format: 111111110xxxxxx0 b data reception bom regular mode the following byte format is assumed (the left most bit is received first): 111111110xxxxxx0 b the signalling controller uses the first two ff h bytes for synchronization, the next byte is stored in the receive fifo (first bit received: lsb) if it starts and ends with a ?0?, that is the receiver automatically removes the ff h synchronization byte. bytes starting or ending with a ?1? are not stored. if the message word 7e h (similar to hdlc flag) is received or when more than four times ff h is received byte sampling is stopped and a ?receive message end? interrupt vector is generated. byte sampling starts again when the synchronization byte ff h is received two times. after detecting 32 bits of ?1?s, byte sampling is stopped, the receive status byte marking the end of a bom frame is stored in the receive fifo and a ?bom idle? interrupt is generated. the same interrupt is generated when not eight consecutive ones where received in 32 bits. data reception bom filter mode in bom filter mode the received bom data is validated and then filtered. if same valid bom pattern is received for 7 out of 10 patterns, then bom data is written to the receive fifo along with the status byte indicating that filtered bom data was received. filtered bom mode will be exited if one of the following conditions occurs: ? 4 valid bom patterns are consecutively received but none of these equals the bom data received earlier. ? 4 times idle pattern is received. 4.6.3 signalling controller fifo operation access to the fifo?s of the signalling controllers is handled via registers. the corresponding fifo?s for receive and transmit direction of the c-bit parity path
peb 3445 e functional description data sheet 55 2001-06-29 maintenance data link channel are named prff and pxff respectively. the fifos of the far end alarm and control channel are named frff and fxff. fifo status and commands are exchanged using the port status registers ppsr (fpsr) and the handshake register phnd (fhnd). the c-bit parity path maintenance data link channel supports an external dma controller via the signals drr , rme or drt and txme . additional interrupts inform the system software about protocol status and fifo status. 4.6.3.1 interrupt driven microprocessor operation receive direction in receive direction there are different interrupt indications associated with the reception of data: ? a ?receive pool full? (rpf) interrupt indicates that a data block can be read from the receive fifo and the received message is not yet complete. it is generated, when the amount of data bytes has reached the programmed threshold. ? a ?receive message end? (rme) or ?receive message idle? interrupt indicates that the reception of one message is completed. after this interrupt system software has to read the corresponding port status register in order to get the number of bytes stored in the receive fifo. this number includes the status byte which is written into the receive fifo as the last byte after the received frame. the status byte includes information about the crc result, valid frame indication, abort sequence or data overflow. the format of the status byte is shown in the table below: smode receiver status mode stat receive fifo status this bit field reports the status of the data stored in the receive fifo. the content of the status byte is dependent on the channel. 7654 0 smode(1:0) 0 stat(4:0) c-bit parity path maintenance data link far end alarm and control channel 00000 b valid hdlc frame bom filtered data declared 00001 b receive data overflow bom data available 00010 b receive abort flag 7e h received
peb 3445 e functional description data sheet 56 2001-06-29 note: for a description of the status information refer to page 165 and page 177 . after the received data has been read from the fifo, the receive fifo has to be released by the cpu with the command ?receive message complete? (fhnd.rmc, phnd.rmc). the cpu has to process a ?receive pool full? interrupt and issue the ?receive message complete? command before the second page of the fifo becomes full. otherwise a ?receive data overflow? condition will occur. this time is dependent on the threshold programmed (smaller threshold results in shorter time). ? figure 10 interrupt driven reception sequence example (32-byte receive threshold) transmit direction in the transmit direction after checking the transmit fifo status by polling the transmit fifo write enable bit (fpsr.xfw, ppsr.xfw) or after a ?transmit pool ready? interrupt, up to 32 bytes may be written to the transmit fifo (bit field fxff.xfifo, pxff.xfifo) by the cpu. transmission of a frame can be started by issuing a ?start transmission? command (see register fhnd on page 167 for far end alarm and control channel and register phnd on page 179 for c-bit parity path maintenance data 00011 b not octet bom filtered data undeclared 00100 b crc error bom idle 00101 b channel off n/a c-bit parity path maintenance data link far end alarm and control channel rd 32 bytes rd 32 bytes rd 15 bytes rd rbc rd status rpf rpf rme rmc rmc 32 bytes 32 bytes 15 bytes rmc receive frame (79 bytes) fdl channel local bus interface
peb 3445 e functional description data sheet 57 2001-06-29 link). if the transmit command does not include a ?transmit message end? indication (fhnd.xme, phnd.xme), the signalling controller will repeatedly request for the next data block by means of a xpr interrupt as soon as the transmit fifo becomes free. this process will be repeated until the local cpu writes the last bytes to the transmit fifo. end of transmission is by issuing the command ?stop transmission?. in case of c-bit parity path maintenance data link channel crc and closing flag sequence is appended after the last byte was sent. c-bit parity path maintenance data link channel only: consecutive frames may share a flag (enabled via bit pxcr.sf) or may be transmitted as back-to-back frames, if service of transmit fifo is quick enough. in case that no more data is available in the transmit fifo prior to the arrival of phnd.xme, the transmission of the frame is terminated with an abort sequence and the cpu is notified via a ?transmit data underrun? interrupt (xdu). the frame may also be aborted per software by setting the xab bit in the handshake register phnd. in case of messages longer than 32 bytes the transmit fifo has to be filled up in blocks of 32 bytes. the last block of the message can be smaller than 32 bytes. if the transmit fifo is not filled up in time a transmit abort (c-bit parity path maintenance data link) is inserted or gaps between bom messages (far end alarm and control channel) may occur. ? figure 11 interrupt driven transmit sequence example note: data bus is 16 bit wide. in the given example writing 32 bytes requires 16 write accesses. writing 15 bytes requires 8 accesses. wr 15 bytes wr 32 bytes xtf 32 bytes 32 bytes 15 bytes xtf transmit frame (79 bytes) fdl channel local bus interface wr 32 bytes xtf+xme xpr xpr xpr alls
peb 3445 e functional description data sheet 58 2001-06-29 4.6.3.2 dma supported data transmission the c-bit parity path maintenance data link channel supports additionally dma signals to optimize data transfers to and from the internal fifos. request signals for transmit and receive direction indicate free respectively available channel data. the rme (receive message end) signal and the txme (transmit message complete) signal indicates the end of a message. receive direction data reception can be initiated by enabling the hdlc controller and setting the dma functionality in register prcfg. as soon as there is a data byte in the receiver the te3- mux autonomously requests a data transfer by activating the drr line. this indicates to the dma controller to read a data byte out of the receive fifo prff. this sequence continuous until the last byte is transferred via the dma controller. the last byte in the receive fifo is always the status byte which contains the frame status information, e.g. ?receive abort? or ?crc error?. when the last byte of a message was read out of the receive fifo the signal rme is asserted to indicate that the port status register ppsr needs to be read in order to free the internal buffer. ? figure 12 dma supported receive sequence transmit direction prior to data transmission the hdlc controller has to be enabled and the dma support must be activated via the register pxcfg. as long as there is free space in the transmit fifo the signalling controller requests data by asserting the drt line which indicates that the external dma controller can write data to the transmit fifo. while writing the last byte of a message the external dma must assert the signal txme , that is the signal read ppsr receive frame (8 bytes) c-bit parity path main- tenance data link local bus interface enable dma d0 d1 d2 d3 d4 d5 crc crc flag rd d0 (prff) drr rd d5 (prff) drr drr rd status (prff) xme
peb 3445 e functional description data sheet 59 2001-06-29 must be asserted while the data byte is on the microprocessor bus. then the next data transfer is the first byte of a new message. the TE3-MUX automatically appends the crc and the flags between messages. ? figure 13 dma supported transmit sequence transmit message (8 bytes) c-bit parity path main- tenance data link local bus interface enable dma wr d0 (pxff) drt drt wr d5 (pxff) set xme drt d0 d1 d2 d3 d4 d5 crc crc flag wr data (pxff) transmit message (8 bytes) 2nd message
peb 3445 e functional description data sheet 60 2001-06-29 4.7 test unit the test unit of the TE3-MUX incorporates a test pattern generator and a test pattern synchronizer which can be attached to different test points as shown in figure 14 . controlled by a small set of registers it can generate and synchronize to polynomial pseudorandom test patterns or repetitive fixed length test patterns. test patterns can be generated in the following modes: ?framed ds3 ? unframed ds2 ?framed ds2 ? unframed ds1/e1 ?framed ds1/e1 note: when the test unit is operated in framed ds1 mode, the bit error rate must be below 1/100. ? figure 14 test unit access points in pseudorandom test mode the receiver tries to achieve synchronization to a test pattern which satisfies the programmed receiver polynomial. in fixed pattern mode it synchronizes to a repetitive pattern with a programmable length. an all ?1? pattern or an all ?0? pattern, which satisfies this condition, is flagged. measurement intervals as well as receiver synchronization can be controlled by the user. when a test is finished an interrupt is generated and the bit count and the bit error count are readable. ds3 framer ds2 framer ds2 framer ds2 framer m23 (de)multi- plexer m12 m12 test unit test mode select test port select test port select 06 06 test port select 027 to ds1/e1 framer
peb 3445 e functional description data sheet 61 2001-06-29 ? figure 15 pattern generator bit error insertion the test unit provides the optional capability to insert bit errors in the range of 10 -7 (1 error in 10.000.000 bits) up to 10 -1 bit errors (1 error in 10 bits). external bit error test four of the 32 low speed tributary interfaces can be used for protection switching or to connect an external bit error rate tester to one of the 28 ds1/21e1 tributaries. 1 n-2 x x-1 0 n-1 + n pattern length x feedback tap + bit error insertion feedback in pseudorandon pattern mode only
peb 3445 e functional description data sheet 62 2001-06-29 4.8 interrupt interface special events in the TE3-MUX are indicated by means of a single interrupt output with programmable characteristics (open drain, push-pull, active low/high), which requests the cpu to read status information or to transfer to/from the TE3-MUX. since only one interrupt output is provided the cause of an interrupt must be determined by the external cpu by reading the interrupt status register d3rintv which indicates the interrupt reason and the interrupt source. status changes of the test unit, the ds2 framer or the ds3 framer require a second read of register d3rintc while loopback code changes of the ds2 receiver require a read of register d3rintl. the interrupt pin is deactivated when register d3rintv was read and no further interrupts are pending. as long as further interrupts are pending the interrupt pin remains asserted and the process as described above needs to be repeated until all pending interrupts are resolved.
peb 3445 e interface description data sheet 63 2001-06-29 5 interface description 5.1 local microprocessor interface the local microprocessor interface is a demultiplexed/multiplexed switchable intel or motorola style interface with an 8- or 16-bit bus interface. 5.1.1 intel mode the intel mode supports a 16- or 8-bit bus interface with demultiplexed or multiplexed bus operation. for multiplexed bus operation la(7:0) must be connected to ld(7:0). the TE3-MUX uses the port pins la(7:0) for the 8 bit address and the port pins ld(15:0) for 16/8 bit data or ld(7:0) in 8-bit interface mode. a read/write access is initiated by placing an address on the address bus and then asserting lcs . the external processor then activates the respective command signal (lrd , lwr ). data is driven onto the data bus either by the TE3-MUX (for read cycles) or by the external processor (for write cycles). after a period of time, which is determined by the access time to the internal registers valid data is placed on the bus. in multiplexed bus operation a falling edge of lale indicates a valid address on la(7:0) and the corresponding byte enable on lbhe . if operated in demultiplexed operated lale must be connected to v dd3 . note: lcs need not to be deasserted between two subsequent cycles to the same device. read cycles input data can be latched and the command signal can be deactivated now. this causes the TE3-MUX to remove its data from the data bus which is then tri-stated again. write cycles the command signal can be deactivated now. if a subsequent bus cycle is required, the external processor can place the respective address on the address bus. table 5 data bus access 16-bit intel mode lbhe la(0) register access data pins used 0 0 word access (16 bit) ld(15:0) 0 1 byte access (8 bit), odd address ld(15:8) 1 0 byte access (8 bit), even address ld(7:0) 1 1 no data transfer -
peb 3445 e interface description data sheet 64 2001-06-29 ? figure 16 intel bus mode (demultiplexed bus operation) ? figure 17 intel bus mode (multiplexed bus operation) address address data data read cycle (16 bit) write cycle (8 bit) la(7:0) lcs lrd lwr ld(15:0) lbhe addr. data data read cycle (16 bit) write cycle (8 bit) la(7:0) ld(15:0) lcs lrd lwr lbhe addr. lale
peb 3445 e interface description data sheet 65 2001-06-29 5.1.2 motorola mode the motorola bus mode supports a 16- or 8-bit bus interface with demultiplexed or multiplexed bus operation. for multiplexed bus operation la(7:0) must be connected to ld(7:0). the TE3-MUX uses the port pins la(7:0) for the 8 bit address and the port pins ld(15:0) for 16/8 bit data or ld(7:0) in 8-bit interface mode. a read/write access is initiated by placing an address on the address bus and asserting lcs together with the command signal lrdwr (see ?motorola bus mode (demultiplexed bus operation)? on page 66 ). the data cycle begins when the signal lds is asserted. data is driven onto the data bus either by the TE3-MUX (for read cycles) or by the external processor (for write cycles). after a period of time, which is determined by the access time to the internal registers valid data is placed on the bus. in multiplexed bus operation a falling edge of lale indicates a valid address on la(7:0)and the corresponding byte enable signal on lble . if operated in demultiplexed bus mode lale must be connected to v dd3 . note: lcs need not to be deasserted between two subsequent cycles to the same device. read cycles input data can be latched and the data strobe signal can be deactivated now. this causes the TE3-MUX to remove its data from the data bus which is then tri-stated again. write cycles the data strobe signal can be deactivated now. if a subsequent bus cycle is required, the external processor can place the respective address on the address bus. table 6 data bus access 16-bit motorola mode lble la(0) register access data pins used 0 0 word access (16 bit) ld(15:0) 0 1 byte access (8 bit), even address ld(15:8) 1 0 byte access (8 bit), odd address ld(7:0) 1 1 no data transfer -
peb 3445 e interface description data sheet 66 2001-06-29 ? figure 18 motorola bus mode (demultiplexed bus operation) ? figure 19 motorola bus mode (multiplexed bus operation) address address data data read cycle (8 bit) write cycle (16 bit) la(7:0) lds lrdwr ld(15:0) lble lcs addr. address data data read cycle (8 bit) write cycle (16 bit) la(7:0) ld(15:0) lds lrdwr lble lcs addr. lale
peb 3445 e interface description data sheet 67 2001-06-29 5.2 serial interface timing 5.2.1 ds3 interface the ds3 interface of the TE3-MUX consists of one receive port and one transmit port. the receive port provides a clock input (rclk44) and one (rd44) or two data inputs (rd44p, rd44n) for unipolar or dual-rail input signals. receive data can be sampled on the rising or falling edge of the receive clock. in transmit direction the port interface consists of two clock signals, the transmit clock input tclk44 and a clock output signal tclko44. the data signals consists of one (td44) or two data outputs (td44p, td44n) for unipolar or dual-rail output signals. the transmit port can be clocked by the receive clock rclk44 or by the transmit clock tclk44. the selected clock is provided as an output on tclko44. transmit data is updated on the rising or falling edge of tclko44. the TE3-MUX provides two additional serial interfaces, one for ds3 overhead bit access and one for ds3 stuff bit access (m13 asynchronous format only). the overhead access is provided via an overhead clock signal (rovhck, tovhck), an overhead data signal (rovhd, tovhd) and an synchronization signal (rovhsyn , tovhsyn ) which marks the x overhead bit of the first subframe of a ds3 signal. in transmit direction the overhead enable signal (tovhden) marks those bits which shall be inserted in the overhead bits of the ds3 signal. overhead signals are updated on the falling edge or sampled on the rising edge of the corresponding overhead clock. see figure 20 and figure 21 for details. ? figure 20 receive overhead access x 84 data bits f 1 f 1 c 11 84 data bits 84 data bits rd44 rclk44 f 1 x rovhck rovhd rovhsyn 7 th subframe 1 st subframe f 1
peb 3445 e interface description data sheet 68 2001-06-29 ? figure 21 transmit overhead access the stuff bit access is provided via a receive and transmit stuff bit clock (rsbck, tsbck) and the two stuff bit signals rsbd and tsbd. stuff bits are updated on the falling edge and sampled on the rising edge of the corresponding stuff bit clock. tovhden x 84 data bits f 1 f 1 c 73 84 data bits 84 data bits td44 tclko44 f 1 x tovhck tovhd tovhsyn (output mode) 7 th subframe 1 st subframe f 1 tovhden x 84 data bits f 1 f 1 c 73 84 data bits 84 data bits td44 tclko44 f 1 x tovhck tovhd tovhsyn (input mode) 7 th subframe 1 st subframe f 1 1. transmit overhead bit access (tovhsyn in output mode) 2. transmit overhead bit access (tovhsyn in input mode)
peb 3445 e interface description data sheet 69 2001-06-29 5.2.2 ds1/e1 interface/ds3 system interface dependent on the selected operational mode the TE3-MUX operates in channelized mode, where the m13 multiplexer is enabled, or in unchannelized mode where the m13 multiplexer is disabled. in unchannelized mode the first tributary interface is used to transfer ds3 payload data. 5.2.2.1 ds1/e1 interface in receive direction (ds3 --> ds1/e1) each port consists of a clock output rtc(x) and the corresponding data output rtd(x). the receive clock is nominally a 1.544 mhz (ds1) respectively a 2.048 mhz (e1) clock. due to the demultiplexing and destuffing process this clock contains clock gaps. each port can be mapped independently to any of the 28 tributaries of the t3 signal. in transmit direction (ds1/e1--> ds3) each port consists of a clock input ttc(x) and the corresponding data input ttd(x). this clock is nominally a 1.544 mhz (ds1 mode) respectively a 2.048 mhz (e1) clock. 5.2.2.2 ds3 system interface in unchannelized mode the first ds1/e1 interface is used to transfer ds3 payload data. the ds3 payload clocks are derived from the ds3 receive respectively the ds3 transmit clock. in receive direction the overhead bits are extracted and the receive clock is gapped on those positions which contain the overhead bits. in transmit direction clock #1 (ttc(1)) is switched to output direction and transmit data needs to be provided via ttd(1). ttc(1) is gapped on those positions where the overhead bits need to be inserted by the TE3-MUX.
peb 3445 e interface description data sheet 70 2001-06-29 5.3 jtag interface a test access port (tap) is implemented in the TE3-MUX. the essential part of the tap is a finite state machine (16 states) controlling the different operational modes of the boundary scan. both, tap controller and boundary scan, meet the requirements given by the jtag standard: ieee 1149.1. figure 22 gives an overview about the tap controller. ? figure 22 block diagram of test access port and boundary scan unit if no boundary scan operation is planned trst has to be connected to v ss . tms and tdi do not need to be connected since pull- up transistors ensure high input levels in this case. nevertheless it would be a good practice to put the unused inputs to defined levels. in this case, if the jtag is not used: tms = tck = ?1? is recommended. test handling (boundary scan operation) is performed via the pins tck (test clock), tms (test mode select), tdi (test data input) and tdo (test data output) when the tap controller is not in its reset state, i. e. trst is connected to v dd3 or trst input is open in which case internal pull sets trst to v dd3 . test data at tdi are loaded with a clock signal connected to tck. ?1? or ?0? on tms causes a transition from one controller state to another; constant ?1? on tms leads to normal operation of the chip. an input pin (i) uses one boundary scan cell (data in), an output pin (o) uses two cells (data out, enable) and an i/o-pin (i/o) uses three cells (data in, data out, enable). note that most functional output and input pins of the TE3-MUX are tested as i/o pins in boundary scan, hence using three cells. the boundary scan unit of the TE3-MUX clock generation test access port (tap) tap controller - finite state machine - instruction register (4 bit) - test signal generator clock tck trst tms reset data in tdi test control tdo enable data out clock identification scan (32 bit) boundary scan (n bit) control bus id data out ss data out n . . . . . . 1 2 pins
peb 3445 e interface description data sheet 71 2001-06-29 contains a total of n = 484 scan cells. the desired test mode is selected by serially loading a 4-bit instruction code into the instruction register via tdi (lsb first). extest is used to examine the interconnection of the devices on the board. in this test mode at first all input pins capture the current level on the corresponding external interconnection line, whereas all output pins are held at constant values (?0? or ?1?). then the contents of the boundary scan is shifted to tdo. at the same time the next scan vector is loaded from tdi. subsequently all output pins are updated according to the new boundary scan contents and all input pins again capture the current external level afterwards, and so on. intest supports internal testing of the chip, i. e. the output pins capture the current level on the corresponding internal line whereas all input pins are held on constant values (?0? or ?1?). the resulting boundary scan vector is shifted to tdo. the next test vector is serially loaded via tdi. then all input pins are updated for the following test cycle. sample/preload is a test mode which provides a snapshot of pin levels during normal operation. idcode : a 32-bit identification register is serially read out via tdo. it contains the version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). the lsb is fixed to ?1?. the id code field is set to version : 1 h part number : 0078 h manufacturer : 083 h (including lsb, which is fixed to ?1?) note: since in test logic reset state the code ?0011? is automatically loaded into the instruction register, the id code can easily be read out in shift dr state. bypass : a bit entering tdi is shifted to tdo after one tck clock cycle. clamp allows the state of signals driven from component pins to be determined from the boundary-scan register while the bypass register is selected as the serial path between tdi and tdo. signals driven from the TE3-MUX will not change while the clamp instruction is selected. highz places all of the system outputs in an inactive drive state.
peb 3445 e reset and initialization procedure data sheet 72 2001-06-29 6 reset and initialization procedure since the term ?initialization? can have different meanings, the following definition applies: chip initialization generating defined values in all on-chip registers, rams (if required), flip-flops etc. mode initialization software procedure, that prepares the device to its required operation, i.e. mainly writing on-chip registers to prepare the device for operation in the respective system environment. operational programming software procedures that setup, maintain and shut down operational modes, i.e. initialize logical channel or maintain framing operations on selected ports. 6.1 chip initialization reset phase the hardware reset rst has to be applied to the device. chip input trst must be activated prior to or while asserting rst and should be held asserted as long as the boundary scan operation is not required. during reset: ? all i/os and all outputs are tri-state. ? all registers, state machines, flip-flops etc. are set asynchronously to their reset values and all internal modules are set to their initial state. ? all interrupts are masked. after hardware reset (rst deasserted) the transmit clock tclk44 is assumed to be running. tributary clocks must be low/high or running. the local bus interface goes into its operational state. 6.2 mode initialization after reset the TE3-MUX is configured in c-bit parity mode. system software has to setup the device for the required function.
peb 3445 e register description data sheet 73 2001-06-29 7 register description the register description of the TE3-MUX is divided into two parts, an overview of all internal registers and in the second part a detailed description of all internal registers. 7.1 register overview note: register locations not contained in the following register tables are ?reserved?. in general all write accesses to reserved registers are discarded and read access to reserved registers result in 0000 h (16-bit bus mode) or 00 h (8-bit bus mode). nevertheless, to allow future extensions, system software shall access documented registers only, since writes to reserved registers may result in unexpected behavior. the read value of reserved registers shall be handled as don?t care. unused and reserved bits are marked with a gray box. the same rules as given for register accesses apply to reserved bits, except that system software shall write the documented default value in reserved bit locations. note: the lower 8 bits (bits 7..0) of a register correspond to even address, the upper 8 bits (bits 15..8) correspond to an odd address. table 7 register overview register access address reset value comment page ds3 clock configuration and status register d3clkcs r/w 00 h 00 h ds3 clock configuration and status 78 tuclkc r/w 01 h 00 h test unit clock configuration 80 ds3 transmit control registers d3tcfg r/w 02 h 0000 h transmit configuration 81 d3tcom r/w 04 h 70 h transmit command 83 d3tlpb r/w 05 h 00 h remote ds2 loopback 85 d3tlpc r/w 06 h 00 h transmit loopback code insertion 86 d3tais r/w 07 h 00 h transmit ais insertion 87 d3tfins r/w 08 h 00 h transmit fault insertion control 88 d3ttuc r/w 09 h 00 h transmit test unit control 89 d3tsdl r/w 0a h 01ff h transmit spare data link 90
peb 3445 e register description data sheet 74 2001-06-29 ds3 receive control/status registers d3rcfg r/w 10 h 0000 h receive configuration 91 d3rcom r/w 12 h 00 h receive command 94 d3rap r/w 13 h 00 h alarm timer parameters 96 d3rimsk r/w 14 h 0fff h receive interrupt mask 97 d3resim r/w 16 h 00 h receive error simulation 98 d3rtuc r/w 17 h 00 h receive test unit control 99 d3rstat r 18 h 0001 h receive status 100 d3rlpcs r 1a h 00 h receive loopback code status 103 d3rsdl r 1c h 01ff h receive spare data link 104 d3rcve r/w 1e h 0000 h receive b3zs code violation error counter 105 d3rexz r/w 2e h 0000 h receive excessive zero counter 105 d3rfec r/w 20 h 0000 h receive framing error counter 106 d3rpec r/w 22 h 0000 h receive parity error counter 106 d3rcpec r/w 24 h 0000 h receive path parity error counter 107 d3rfebec r/w 26 h 0000 h receive febe error counter 107 d3rintv r 28 h 00 h interrupt vector 108 d3rintc r 2a h 0000 h interrupt status 111 d3rintl r 2c h 00 h interrupt loopback code status 112 ds2 transmit control registers d2tsel r/w 30 h 00 h ds2 transmit group select 113 d2tcfg r/w 31 h 00 h transmit configuration 114 d2tcom r/w 32 h 00 h transmit command 115 d2tlpc r/w 33 h 00 h remote ds1/e1 loopback loopback code insertion 116 d2ttm0 r/w 34 h 00 h tributary map registers 117 d2ttm1 r/w 35 h 00 h d2ttm2 r/w 36 h 00 h d2ttm3 r/w 37 h 00 h register access address reset value comment page
peb 3445 e register description data sheet 75 2001-06-29 ds2 receive control registers d2rsel r/w 40 h 00 h ds2 receive group select 118 d2rcfg r/w 41 h 00 h receive configuration 119 d2rcom r/w 42 h 00 h receive command 121 d2rimsk r/w 43 h 00 h receive interrupt mask 123 d2rtm0 r/w 44 h 00 h tributary map registers 124 d2rtm1 r/w 45 h 00 h d2rtm2 r/w 46 h 00 h d2rtm3 r/w 47 h 00 h d2rlais r 48 h 00 h local ds1/e1 loopback ais insertion register 125 d2rstat r 49 h 00 h receive status 126 d2rlpcs r 4a h 00 h receive loopback code status 128 d2rap r/w 4b h 00 h alarm timer parameters 129 d2rfec r/w 4c h 0000 h receive framing bit error counter 131 d2rpec r/w 4e h 0000 h receive parity bit error counter (g.747) 131 test unit transmit registers tutcfg r/w 50 h 0000 h transmit configuration 132 tutcom w 52 h 00 h transmit command 133 tuteir r/w 53 h 00 h transmit error insertion rate 135 tutfp0 r/w 54 h 0000 h transmit fixed pattern 136 tutfp1 r/w 56 h 0000 h test unit receive registers turcfg r/w 58 h 0000 h receive configuration 137 turcom w 5a h 00 h receive command 139 turermi r/w 5b h 00 h receive error measurement interval 141 turimsk r/w 5c h 1f1f h receive interrupt mask 142 turstat r 5e h 0001 h receive status 143 register access address reset value comment page
peb 3445 e register description data sheet 76 2001-06-29 turbc0 r 60 h 0000 h receive bit counter 145 turbc1 r 62 h 0000 h turec0 r 64 h 0000 h receive error counter 147 turec1 r 66 h 0000 h turfp0 r 68 h 0000 h receive fixed pattern 149 turfp1 r 6a h 0000 h test unit framer registers tutfcfg r/w 70 h 00 h transmit framer configuration 150 tutfcom r/w 71 h 00 h transmit framer command 152 turfcfg r/w 74 h 00 h receive framer configuration 153 turfcom r/w 75 h 00 h receive framer command 155 turfstat r 76 h 00 h receive framer status register 156 turffec r 78 h 0000 h receive framing error counter 157 turfcec r 7a h 0000 h receive framer crc error counter 158 turfebc r 7c h 0000 h receive framer errored block counter 159 far end alarm and control channel (bom) frcfg r/w 80 h 0000 h receive configuration register 160 frff r 82 h 0000 h receive fifo 162 fxcfg r/w 84 h 00 h transmit configuration register 163 fxff w 86 h 0000 h transmit fifo 164 fpsr r 88 h 2000 h port status register 165 fhnd w 8a h 0000 h handshake register 167 fmsk r/w 8c h 00 h interrupt mask register 170 c-bit path maintenance channel (hdlc) prcfg r/w 90 h 0000 h receive configuration register 171 prff r 92 h 0000 h receive fifo 173 pxcfg r/w 94 h 0000 h transmit configuration register 174 pxff w 96 h 0000 h transmit fifo 176 ppsr r 98 h 2000 h port status register 177 register access address reset value comment page
peb 3445 e register description data sheet 77 2001-06-29 phnd w 9a h 0000 h handshake register 179 pmsk r/w 9c h 00 h interrupt mask register 181 register access address reset value comment page
peb 3445 e register description data sheet 78 2001-06-29 7.2 detailed register description 7.2.1 ds3 control and status registers d3clkcs ds3 clock configuration and status register access : read/write address : 00 h reset value : 00 h rca receive clock activity this bit monitors the receive clock activity (rclk44). 0 no receive ds3 clock since last read of this register. 1 at least one receive ds3 clock since last read of this register. tca transmit clock activity this bit monitors the transmit clock activity (tclk44). 0 no transmit ds3 clock since last read of this register. 1 at least one transmit ds3 clock since last read of this register. rrx reset receiver this bit resets the receiver. 0 normal operation. 1 reset ds3 receiver. this bit is self clearing. rtx reset transmitter this bit resets the transmitter. 0 normal operation. 1 reset ds3 transmitter. this bit is self clearing. 76543210 0 rca tca rrx rtx t2rl r2tl txlt
peb 3445 e register description data sheet 79 2001-06-29 t2rl transmit to receive loop (local ds3 loopback) this bit enables the local ds3 loop where the outgoing ds3 bit stream is mirrored to the ds3 input. 0 disable local loop. 1 enable local loop. r2tl receive to transmit loop (remote ds3 loopback) this bit enables the remote ds3 line loop where the complete incoming ds3 bit stream is mirrored to the transmitter. 0 disable remote loop. 1 enable remote loop. txlt transmit loop timing mode this bit enables ds3 looped timing where the transmitter uses the receivers ds3 input clock. 0 disable looped timing. 1 enabled looped timing.
peb 3445 e register description data sheet 80 2001-06-29 tuclkc test unit clock configuration register access : read/write address : 01 h reset value : 00 h rtur reset test unit receiver this bit resets the test unit receiver. 0 normal operation. 1 reset receiver (automatically removed). this bit is self clearing. tul test unit transmit to receive loop this bit switches a local loop from the test unit transmitter to the test unit receiver. while operating in loop mode the test unit is operated with tclk44. 0 normal operation. 1 test unit transmitter output connected to test unit receiver input. 710 0 0 0 0 0 0rturtul
peb 3445 e register description data sheet 81 2001-06-29 d3tcfg ds3 transmit configuration register access : read/write address : 02 h reset value : 0000 h itrck invert ds1/e1 interface clock this bit sets the clock edge for data sampling on the low speed interfaces. 0 sample data on the falling edge of ttc(x). 1 sample data on the rising edge of ttc(x). itrd invert ds1/e1 data this bit enables inversion of sampled data. 0 no inversion of data sampled on ttd(x). 1 invert data sampled on ttd(x). fam tovhsyn mode this bit switches between input mode and output mode of the signal pin tovhsyn . if tovhsyn is operated in input mode it marks the position of the x-bit. therefor the outgoing ds3 frame is aligned to tovhsyn . if tovhsyn is switched to output mode tovhsyn is asserted when the x-bit needs to be inserted via the transmit overhead interface. 0 tovhsyn switched to input. 1 tovhsyn switched to output. itck invert ds3 transmit clock this bit sets the clock edge on which transmit data td44p/td44n is updated with respect to the transmit clock tclko44. 0 update transmit data on the rising edge of the transmit clock. 1 update transmit data on the falling edge of transmit clock. 15 109876543210 0 0 0 0 0 itrck itrd fam itck itd utd aisc lpc(1:0) fpl cbp
peb 3445 e register description data sheet 82 2001-06-29 itd invert ds3 transmit data this bit enables inversion of ds3 transmit data. 0 transmit data is logic high (not inverted). 1 transmit data is logic low (inverted). utd unipolar data mode this bit sets the port mode to dual-rail mode or unipolar mode. 0 b3zs (dual rail data). 1 unipolar mode (single rail data). aisc ais code type this bit field sets the ais code. 0 set ais to ?1010... ? between overhead bits, c-bits all ?0?s. the x- bits needs to be set via d3tcom.txbit. 1 set ais to unframed all ?1?s (non-standard). lpc loopback code. this bit field selects the c-bit which will be inverted when loopback requests are transmitted. 00 invert 1 st c-bit. 01 invert 2 nd c-bit. 10 invert 3 rd c-bit. fpl full payload mode this bit enables the m23 multiplex operation or the full payload rate format. 0 enable m23 multiplex operation. payload is formed by interleaving 7 asynchronous ds2 tributaries. 1 enable full payload rate format. the payload is one single, high speed data stream without stuffing. cbp c-bit parity mode this bit enables m13 asynchronous mode or c-bit parity mode. 0 m13 asynchronous mode. 1 c-bit parity mode.
peb 3445 e register description data sheet 83 2001-06-29 d3tcom ds3 transmit command register access : read/write address : 04 h reset value : 70 h taic transmitted aic-bit this bit sets the value to be transmitted in the ds3 overhead bit of block 3, subframe 1. this function is available in c-pit parity format only. 0 aic-bit = ?0?. 1 aic-bit = ?1?. tn r b transmitted n r -bit this bit sets the value to be transmitted in the ds3 overhead bit of block 5, subframe 1. this function is available in c-pit parity format only. 0n r -bit = ?0?. 1n r -bit = ?1?. txbit transmitted x-bits this bit sets the value to be transmitted in the ds3 overhead bit of block 1, subframes 1 and 2. txbit is synchronized to the ds3 multiframe. both x-bits in a multiframe are guaranteed identical. software should limit changes to maximum of 1 per second. note: setting txbit to ?0? results in transmission of remote alarm indication even when sidle, saisa or sais are set. 0 x-bit = ?0?. 1 x-bit = ?1?. 76543210 0taictn r b txbit sidlesaisa sais 0
peb 3445 e register description data sheet 84 2001-06-29 sidle send ds3 idle code this bit enables transmission of the ds3 idle code (?1100? between overhead bits, c-bits all ?0?s). the x-bits must be set to ?1? independently by setting txbit to ?1?. 0 normal operation. 1 send ds3 idle code. saisa send ais in ds3 output and on ds3 loop this bit enables transmission of ais on the ds3 output. if the ds3 is additionally switched to local ds3 loopback mode the ds3 signal including ais is mirrored to the receiver. the ais code transmitted depends on d3tcfg.aisc. the x-bits must be set to ?1? independently by setting txbit to ?1?. 0 normal operation. 1 enable transmission of ais. sais send ais at ds3 output this bit enables transmission of ais on the ds3 output. if the ds3 signal is switched into local ds3 loopback mode the ds3 signal without ais code is mirrored to the ds3 receiver. the ais code transmitted depends on d3tcfg.aisc. the x-bits must be set to ?1? independently by setting txbit to ?1?. 0 normal operation. 1 enable transmission of ais.
peb 3445 e register description data sheet 85 2001-06-29 d3tlpb ds3 transmit remote ds2 loopback register access : read/write address : 05 h reset value : 00 h lpb remote ds2 loopback setting lpb(x) enables the remote ds2 loopback of tributary x. in this mode the demultiplexed ds2 tributary is internally looped and multiplexed into the outgoing ds3 signal. 0 normal operation. 1 enable remote ds2 loopback of tributary x. 76 0 0 lpb(6:0)
peb 3445 e register description data sheet 86 2001-06-29 d3tlpc ds3 transmit loopback code insertion register access : read/write address : 06 h reset value : 00 h lpc send loopback setting lpc(x) enables transmission of the loopback code in tributary x of the ds3 signal. the loopback code inserted depends on d3tcfg.lpc. 0 normal operation. 1 enable transmission of loopback code in tributary x. 76 0 0lpc(6:0)
peb 3445 e register description data sheet 87 2001-06-29 d3tais ds3 transmit ais insertion register access : read/write address : 07 h reset value : 00 h aise ais error insertion toggling this bit inserts one ?0? in all ds3 tributaries which transmit ais. ais send ds2 alarm indication signal setting ais(x) enables insertion of the ds2 alarm indication signal in the outgoing tributary x of the ds3 signal. ais is an all ?1? signal. 0 normal operation. 1 enable transmission of ais in tributary x. 76 0 aise ais(6:0)
peb 3445 e register description data sheet 88 2001-06-29 d3tfins ds3 transmit fault insertion control register access : read/write address : 08 h reset value : 00 h finsc fault insertion code. fault insertion is service affecting and is intended for testing only. codes are not self clearing, i.e. errors are continuously generated as indicated until bit cleared. a single febe, p, cp, or code violation is guaranteed to be inserted if the respective code is written and then immediately cleared. 0 normal operation (no fault insertion). 1 insert febe event every multiframe (106 sec). 2 insert p-bit errors every 2nd multiframe (212 sec). 3 insert cp-bit errors every 2nd multiframe (212 sec). 4 insert 4 f-bit errors/multiframe (satisfies 3 out of 15 threshold trigger). 5 insert 5 f-bit errors/multiframe (satisfies 3 out of 7 threshold trigger). 6 insert 3 m-bit errors/multiframe (caution: receiver can frame on emulator). 7 force ds3 output to all ?0?s. 8 insert b3zs violation/multiframe (violation of alternate polarity rule). 9 insert 3 zero string/multiframe (b3zs code word suppressed). 730 0 0 0 0finsc(3:0)
peb 3445 e register description data sheet 89 2001-06-29 d3ttuc ds3 transmit test unit control register access : read/write address : 09 h reset value : 00 h en enable test unit insertion setting this bit enables insertion of the test unit data. 0 normal operation. 1 enable insertion of test unit data. tuds2 test unit ds2 group this bit field selects the ds2 group the test unit is attached to. only valid if tuim is 10 b , 01 b or 00 b . 0..6 selects ds2 group 0..6. tuds1 test unit ds1 tributary this bit field selects the ds1 tributary the test unit is attached to. only valid if tuim is 00 b . the ds2 group is selected via tuds2. 0..3 ds1/e1 tributary tuim bit error rate test unit (tu) insertion mode this bit field selects the interface the test unit is attached to. 00 b insert test stream into ds1/e1 tributary. 01 b insert test stream into ds2 tributary (unframed, bypass m12). 10 b insert test stream into ds2 payload (framed). 11 b insert test stream into ds3 payload (framed). 76 43210 en tuds2(2:0) tuds1(1:0) tuim
peb 3445 e register description data sheet 90 2001-06-29 d3tsdl ds3 transmit spare data link register access : read/write address : 0a h reset value : 01ff h multiframe buffer for spare dl bits transmitted in blocks 3, 5, and 7 of subframes 2, 6, and 7. if enabled, the m13 will generate an interrupt every multiframe to request a refresh of this register. the software must write these registers within 106 sec to avoid an underrun. dl(s)(b) overhead bit for block b of subframe s these bits store the dl bits to be transmitted in blocks 3, 5, and 7 of subframes 2, 6, and 7. if enabled, the m13 will generate an interrupt every multiframe to request a refresh of this register. 15 876543210 0 0 0 0 0 0 0 dl77 dl75 dl73 dl67 dl65 dl63 dl27 dl25 dl23
peb 3445 e register description data sheet 91 2001-06-29 d3rcfg ds3 receive configuration register access : read/write address : 10 h reset value : 0000 h note: m13 mode, full payload mode, loopback code, and ais mode are controlled by bits cbp, fpl, lpc, and aisc in register ds3 transmit configuration register d3tcfg. cvm b3zs code word (?00v? or ?10v? acceptance condition) this bit selects the b3zs violations alternate polarity to maintain line balance. 0 convert all b3zs codeword patterns to ?000? regardless of polarity. 1 convert codeword only if alternate violation polarity rule is satisfied. itrck invert tributary clock this bit sets the clock edge for data update on the low speed tributaries. 0 update data on the rising edge of rtc(x). 1 update data on the falling edge of rtc(x). itrd invert tributary data this bit enables inversion of tributary data. 0 no inversion of data provided via rtd(x). 1 invert data provided via rtd(x). od interrupt open drain this bit selects the operating mode of the interrupt pin. 0 open drain. 1 push-pull. 15141312111098 6543210 cvm itrck itrd od il sttm ecm febm 0 aisx mfm mdis ffm irck ird urd
peb 3445 e register description data sheet 92 2001-06-29 il interrupt active level this bit selects the active level of the interrupt pin. 0active low. 1 active high. sttm select transmit tributary monitoring for receive test unit this bit selects the ds1/e1 tributary observed by the test unit receiver. the test unit can be connected to the upstream ds1/e1 tributary (ds1/ e1 tributary going towards the ds3 interface) or to the downstream ds1/ e1 tributary (ds1/e1 tributary coming from the ds3 interface). 0 monitor downstream ds1/e1 tributary. 1 monitor upstream ds1/e1 tributary. ecm error counter mode ds3 errors are counted in background and copied to foreground (error counter registers) when condition selected via ecm is met. 0 counter values are copied to foreground when copy command is executed. see also register ds3com. 1 the counter values are copied to the foreground register in one second intervals. at the same time the background registers are reset to zero. this operation is synchronous with the periodic one second interrupt which alerts software to read the register. febm far end block error (febe) mode this bit selects the event which leads to febe indication. it is available in c-bit parity mode only. 0 receive multiframe parity error. 1 receive multiframe parity error or framing error. aisx ais x-bit check disable this bit disables checking of the x-bit for ais and idle detection. 0 check x-bit. 1 disable check of x-bit.
peb 3445 e register description data sheet 93 2001-06-29 mfm multiframe framing mode this bit selects the m-bit error condition which triggers the ds3 framer to start a new frame search. to enable reframing in case of m-bit errors mdis must be set to ?0?. 0 start new f-frame search if m-bit errors are detected in two out of four consecutive m-frames. 1 start new f-frame search if m-bit errors are detected in three out of four consecutive m-frames. mdis multiframe reframe disable this bit disables reframing due to m-bit errors. 0 enable reframe due to m-bit errors. 1 disable reframe due to m-bit errors. ffm f framing mode this bit selects the f-bit error condition which triggers the ds3 framer to start a new frame search. 0 a new frame search is started when 3 out of 8 contiguous f-bits are in error. 1 a new frame search is started when 3 out of 16 contiguous f-bits are in error. irck invert receive clock this bit sets the clock edge for data sampling. 0 sample data on rising edge of receive clock. 1 sample data on falling edge of receive clock. ird invert receive data this bit enables inversion of receive data. 0 receive data is logic high (not inverted). 1 receive data is logic low (inverted). urd unipolar receive data this bit sets the port mode to dual-rail mode or unipolar mode. 0 b3zs (dual rail data input). 1 unipolar mode (single rail data input).
peb 3445 e register description data sheet 94 2001-06-29 d3rcom ds3 receive command register access : read/write address : 12 h reset value : 00 h c3nc copy ds3 error counters values of ds3 background registers are copied to foreground. background registers are not cleared. command is self clearing and completes before next register access is possible i.e. software can write command and then immediately read the counters without starting a delay timer. note: usage of this function in not recommend in ?one second? error counter mode (d3rcfg.ecm = ?1?). 0 no operation. 1 copy background counters to foreground. c3c copy and clear ds3 error counters values of ds3 background registers are copied to foreground. background registers are cleared. command is self clearing and completes before next register access is possible i.e. software can write command and then immediately read the counters without starting a delay timer. 0 no operation. 1 copy background counters to foreground. clear background counters. note: usage of this function in not recommend in ?one second? error counter mode (d3rcfg.ecm = ?1?). cnca copy error counters only valid for counters which are not operating in ?one second? error counter mode. values of ds2 and ds3 background registers are copied to foreground. background registers are not cleared. command is self 7 43210 0 0 0 c3nc c3c cnca cca frs
peb 3445 e register description data sheet 95 2001-06-29 clearing and completes before next register access is possible i.e. software can write command and then immediately read the counters without starting a delay timer. 0 no operation. 1 copy background counters to foreground. cca copy and clear ds2/ds3 error counters only valid for counters which are not operating in ?one second? error counter mode. values of ds2 and ds3 background registers are copied to foreground. background registers are cleared. command is self clearing and completes before next register access is possible i.e. software can write command and then immediately read the counters without starting a delay timer. 0 no operation. 1 copy background counters to foreground. clear background counters. frs force resynchronization this bit enables a new frame search on the ds3 input. the command is self clearing after frame search has begun. 0 normal operation. 1 force new frame search.
peb 3445 e register description data sheet 96 2001-06-29 d3rap ds3 receive alarm timer parameters register access : read/write address : 13 h reset value : 00 h ais ais criteria this bits sets the error rate for ais detection. declaration of ais depends on value defined in bit field cv. 0 ais is recognized when the alarm indication signal is received with less than 8 errors per multiframe. 1 ais is recognized when the alarm indication signal is received with less than 15 errors per multiframe. cv counter value this bit specifies the number of frames when the TE3-MUX declares ais, red or idle. 0..63 counter value. 75 0 ais 0 cv(5:0)
peb 3445 e register description data sheet 97 2001-06-29 d3rimsk ds3 receive interrupt mask register access : read/write address : 14 h reset value : 0fff h this register provides the interrupt mask for ds3 status interrupts and ds3 loopback code interrupts. see register d3rstat and d3rlpcs for interrupt conditions. the following definition applies: 1 the corresponding interrupt will not be generated by the device. 0 the corresponding interrupt will be generated. rsdl mask ?receive spare data link transfer buffer full? tsdl mask ?transmit spare data link transfer buffer empty? lpcs mask ?loopback code status? (flagged in d3rlpcs) 1sec mask ?1 second interrupt? n r mask ?n r -bit image? (c-bit parity mode only) aic mask ?aic-bit image? (c-bit parity mode) xbit mask ?x-bit image? idles mask ?ds3 idle signal state? aiss mask ?ds3 alarm indication signal state? reds mask ?ds3 red alarm state? loss mask ?ds3 input signal state? fas mask ?ds3 frame alignment state? 15 11109876543210 0 0 0 0 rsdl tsdl lpcs 1sec n r aic xbit idles aiss reds loss fas
peb 3445 e register description data sheet 98 2001-06-29 d3resim ds3 receive error simulation register access : read/write address : 16 h reset value : 00 h ftmr fast timer this bit enables alarm timer test function (manufacturing test only). 0 normal operation. 1 test operation. ds3 red/ais/idle timer period reduced by 56. ds2 read/ais timer period reduced by 24. second interrupt period reduced to 140 sec esimc error simulation code this bit enables error simulation. during error simulation the device generates error interrupts and error status messages. nevertheless the service is not affected. 0 normal operation (no error simulation). 1 simulate one f-bit error/multiframe (106 sec). 2 simulate m-bit error in every other multiframe. 3 simulate febe event/multiframe (106 sec). 4 simulate p/cp event/multiframe (106 sec). 5 simulate loss of ds3 input (all zeros). 6 simulate b3zs code violations. 7 simulate loss of receive clock. 7420 0 0 0ftmr 0 esimc(2:0)
peb 3445 e register description data sheet 99 2001-06-29 d3rtuc ds3 receive test unit control register access : read/write address : 17 h reset value : 00 h en enable test unit receive clock this bit enables the receive clock of the test unit. the clock speed is dependent on the selected test mode. 0 receive clock disabled. 1 receive clock enabled. tuds2 test unit ds2 group this bit field selects the ds2 group the test unit is attached to. only valid if turm is 10 b , 01 b , or 00 b . 0..6 selects ds2 group 0..6. tuds1 test unit ds1/e1 tributary this bit field selects the ds1/e1 tributary the test unit is attached to. only valid if turm is 00 b . the ds2 group is selected via tuds2. 0..3 ds1/e1 tributary turm test unit receive mode this bit field selects the interface the test unit is attached to. 00 b ds1/e1 tributary 01 b ds2 tributary (unframed, bypass m12) 10 b ds2 payload (framed) 11 b ds3 payload (framed) 76 43210 en tuds2(2:0) tuds1(1:0) turm(1:0)
peb 3445 e register description data sheet 100 2001-06-29 d3rstat ds3 receive status register access : read address : 18 h reset value : 0001 h each bit in the ds3 framer receive status register declares a specific condition dependent on the selected modes. the following convention applies to the individual bits: 0 the named status is not or no longer existing. 1 the named status is currently effective. except for cofa every bit can be used to generate an interrupt. interrupts can be masked in register d3rimsk. rsdl receive spare data link buffer full this bit indicates that the spare data link receive buffer (register d3rsdl) is full. tsdl transmit spare data link buffer empty this bit indicates that the spare data link transmit buffer (register d3tsdl) is empty. lpcd loopback code detected this bit indicates changes in register d3rlpcs. 1sec 1 second flag this bit toggles every second synchronously with the one second interrupt. it can be used by software to synchronize 1 second events when the ?one second interrupt? is masked. 1514131211109876543210 0 0 0 rsdl tsdl lpcd 1sec n r / aicc aic xbit idles aiss reds loss cofa fas
peb 3445 e register description data sheet 101 2001-06-29 n r /aicc n r -bit image (c-bit parity format only) this bit contains an image of the ds3 frame overhead bit in block 5 of subframe 1. it is updated only if its state persists for 3 multiframes and ds3 frame is aligned. aic-bit changed (m13 asynchronous format) this bit indicates a change of the aic-bit (first c-bit of the first subframe) since the last read of this register. aic aic-bit image (ds3 frame overhead bit in block 3 of subframe 1) this bit contains an image of the ds3 frame overhead bit in block 3 of subframe 1. it is updated only if its state persists for 3 multiframes and ds3 frame is aligned. xbit x-bit image (ds3 frame overhead bit in block 1 of subframes 1 and 2) this bit contains an image of the ds3 frame overhead bit in block 1 of subframes 1 and 2. it is updated only if both overhead have the same value, when its state persists for 3 multiframes and when the ds3 frame is aligned. idles ds3 idle signal state this bit indicates that the idle pattern (framed ...1100... with c-bits=?0? in subframe 3 and x-bits=?1?) was persistent as per alarm timing parameters defined in register d3rap. idle is considered active in a multiframe when fewer than 15 errors are detected. at 10 -3 error rates, 5 errors per multiframe are typical. the exact time necessary to change the flag could be greater if the fas flag is not constant. the frame alignment state is integrated by incrementing or decrementing a counter at the end of each multiframe when the fas flag is set or cleared respectively. aiss ds3 alarm indication signal state this bit indicates the ais alarm state. ais can be a framed ?..1010..? pattern with c-bits=?0? and x-bits=?1? or an unframed all ?1? pattern. this is determined by d3tcfg.aisc. ais is considered active in a multiframe when fewer than 15 errors are detected and is declared when it was persistent as per alarm timing parameters defined in register d3rap. at 10 -3 error rates, 5 errors per multiframe are typical. the exact time necessary to change the flag could be greater if the fas flag is not constant. the frame alignment state is integrated by incrementing or decrementing a counter at the end of each multiframe when the fas flag is set or cleared respectively.
peb 3445 e register description data sheet 102 2001-06-29 reds ds3 red alarm state (loss of frame alignment) this bit indicates that red alarm was persistent as per alarm timing parameter defined in register d3rap. the red alarm flag nominally changes when loss of frame alignment condition persists for either 32 or 128 multiframes. the exact time necessary to change the flag could be greater if the fas flag is not constant. the frame alignment state is integrated by incrementing or decrementing a counter at the end of each multiframe when the fas flag set or cleared respectively. loss ds3 input signal state this bit indicates that the received ds3 bit stream contained at least 175 consecutive ?0?s. it is deasserted when 59 ?1? bits are detected in 175 clocks (1/3 density). following removal of los, a 10 msec guard timer is started. if a new los occurs, the release condition is extended so that the 1/3 density condition must persist for at least 10 msec. this prevents chatter and excessive interrupts. cofa change of frame alignment this bit indicates a change of frame alignment event. it is set when the ds3 framer found a new frame alignment and when the new frame position differs from the expected frame position. fas ds3 frame alignment state this bit indicates that the ds3 framer is not aligned.
peb 3445 e register description data sheet 103 2001-06-29 d3rlpcs ds3 receive loopback code status register access : read address : 1a h reset value : 00 h lpcd loopback detected lpcd(x) indicates that a loopback request was received. a loopback request for tributary x is indicated by inverting one of the 3 c-bits of the x th subframe. the c-bit is determined by d3tcfg.lpc. a command state change must persist for 5 contiguous multiframes before it will be reported. this function is available in m13 asynchronous mode only. 0 no loopback code being received 1 loopback code being received 76543210 0lpcd(6:0)
peb 3445 e register description data sheet 104 2001-06-29 d3rsdl ds3 receive spare data link register access : read address : 1c h reset value : 01ff h dl(s)(b) overhead bit for block b of subframe s these bits buffer the spare dl bits received in blocks 3, 5, and 7 of subframes 2, 6, and 7. if enabled, the m13 will generate an interrupt every multiframe to synchronize reading of this register. the register must be read within 106 sec to avoid an overrun. 15 876543210 0 0 0 0 0 0 0 dl77 dl75 dl73 dl67 dl65 dl63 dl27 dl25 dl23
peb 3445 e register description data sheet 105 2001-06-29 d3rcve ds3 receive b3zs code violation error counter access : read/write address : 1e h reset value : 0000 h cve(15:0) b3zs code violation errors error counter mode (clear on read or errored second) depends on register d3rcfg.ecm. register d3rcve counts line code violations. the error counter will not be incremented during asynchronous state. d3rexz ds3 receive excessive zeroes counter access : read/write address : 2e h reset value : 0000 h exz(15:0) excessive zeroes error counter mode (clear on read or errored second) depends on register d3rcfg.ecm. violations are 3 zero strings. the error counter will not be incremented during asynchronous state. 15 0 cve(15:0) 15 0 exz(15:0)
peb 3445 e register description data sheet 106 2001-06-29 d3rfec ds3 receive framing bit error counter access : read/write address : 20 h reset value : 0000 h fec(15:0) framing bit error counter error counter mode (clear on read or errored second) depends on register d3rcfg.ecm. count of f-bit and m-bit errors. errors are not counted in out of frame state. d3rpec ds3 receive parity error counter access : read/write address : 22 h reset value : 0000 h pe(15:0) parity bit error counter error counter mode (clear on read or errored second) depends on register d3rcfg.ecm. count of parity errors (p-bits in ds3 overhead bits). the p-bit is duplicated in the ds3 frame structure but only single error maximum is counted per multiframe. errors are not counted in out of frame state. 15 0 fec(15:0) 15 0 pe(15:0)
peb 3445 e register description data sheet 107 2001-06-29 d3rcpec ds3 receive path parity error counter access : read/write address : 24 h reset value : 0000 h cpe(15:0) path parity error counter error counter mode (clear on read or errored second) depends on register d3rcfg.ecm. count of path parity errors (cp bits in ds3 c-bit parity overhead bits). cp-bits are triplicated in the ds3 frame structure but only single error maximum is counted per multiframe. errors are not counted in out of frame state. d3rfebec ds3 receive febe error counter access : read/write address : 26 h reset value : 0000 h febe(15:0) febe error events error counter mode (clear on read or errored second) depends on register d3rcfg.ecm. this register counts the occurrence of a received ?not all ?1?s?. febe-bits are triplicated in the ds3 frame structure but only one single error maximum is counted per multiframe. errors are not counted in out of frame state. 15 0 cpe(15:0) 15 0 febe(15:0)
peb 3445 e register description data sheet 108 2001-06-29 d3rintv interrupt vector register access : read address : 28 h reset value : 00 h four vectors are defined and differentiated by the type field (bits 6 and 7). the interrupt status information contained in the status field (bits 5 down to 0) is dependent on the type information. type interrupt type information this bit field defines the content of the following interrupt status field. 00 this code defines loopback code changes or status changes of the ds2 or ds3 framer. subsequently the changes can be read in register d3rintc or d3rintl. 01 this code defines general status informations. 10 this code defines interrupts of the far end alarm and control channel. 11 this code defines interrupts of the c-bit parity path maintenance data link channel. status status information the status information is dependent on the value of the type bit field. the following section defines the meaning of the status bits: lbr loopback code status change this bit indicates a change of received ds3 or ds2 loopback code status. the loopback code status is shown in register d3rintl. the related port is indicated in bit field gn. 76543210 type status 00 0 lbr sr gn(2:0) 01 0 0 rdl tdl tu 1s 10 alls xdu xpr rpf rme rmi 11 0
peb 3445 e register description data sheet 109 2001-06-29 sr status register change this bit indicates a change in ds3 or ds2 status. the status is shown is register d3rintc. the related port is indicated in bit field gn. gn group number this bit field indicates the port where a status change or loopback code change occurred. 0..6 status change of ds2 framer 0..6. 7 status change of ds3 framer. rdl receive spare data link buffer full this bit indicates that new dl bits have been received in register d3rsdl. if enabled it is generated with every multiframe to synchronize reading of register d3rsdl. tdl transmit spare data link buffer empty this bit indicates that new dl bits shall be written to register d3tsdl. if enabled it is generated with every multiframe to synchronize writing of register d3rsdl. tu test unit status change this bit indicates a status change of the test unit. subsequently the status can be read in register d3rintc. 1s 1 second the ?one second? interrupt is generated every second. alls all sent the ?all sent? interrupt is generated, when the last bit of a frame to be transmitted is completely sent out and xff.xfifo is empty. xdu transmit data underrun the ?transmit data underrun? interrupt is generated, when the transmit fifo of the corresponding channel runs out of data during transmission of a frame. the protocol controller terminates the affected frame. xpr transmit pool ready the ?transmit pool ready? interrupt is generated, when a new data block of up to 32 bytes can be written to transmit fifo. ?transmit pool ready? is the fastest way to access the transmit fifo. it has to be used for transmission of long frames, back-to-back frames or frames with shared flag. rpf receive pool full this bit is set, when the receive threshold is reached and data has to be read from the receive fifo. the frame is not yet completely received.
peb 3445 e register description data sheet 110 2001-06-29 rme receive message end this bit is set, when one complete message of length less than 32 bytes or the last part of a frame is stored in the receive fifo. the number of bytes in rff.rfifo can be determined reading the port status register f/ppsr. rmi receive message idle/incorrect this bit is set, when four flags (ff h ) or no eight consecutive ?1?s are detected within 32 bits.
peb 3445 e register description data sheet 111 2001-06-29 d3rintc interrupt status register access : read address : 2a h reset value : 0000 h this register must be read after register d3rintv and dependent on the content of register d3rintv it contains a copy of register d3rstat, d2rstat or turstat.
peb 3445 e register description data sheet 112 2001-06-29 d3rintl interrupt loopback code status register access : read address : 2c h reset value : 0000 h this register must be read after register d3rintv and dependent on the content of register d3rintv this register contains a copy of register d3rlpcs or d2rlpcs.
peb 3445 e register description data sheet 113 2001-06-29 7.2.2 ds2 control and status registers d2tsel ds2 transmit group select register access : read/write address : 30 h reset value : 00 h note: this register is an indirect access register, which must be programmed before accessing the register ds2 transmit registers. gn group number this bit field selects the ds2 group, which can be accessed via the ds2 transmit registers. please refer to section ?tributary mapper? on page 37 for a detailed description of the tributary mapper and to page 117 for programming examples. 0..6 tributary group number. 7 spare line group 720 0 0 0 0 0gn(2:0)
peb 3445 e register description data sheet 114 2001-06-29 d2tcfg ds2 transmit configuration register access : read/write address : 31 h reset value : 00 h lpc loopback code this bit selects the c-bit which will be inverted when loopback requests are transmitted. 00 invert 1 st c-bit. 01 invert 2 nd c-bit. 10 invert 3 rd c-bit. e1 g.747 select this bit selects the operation mode of the low speed multiplexer. 0 select m12 mode (4 ds1 into ds2). 1 select itu-t g.747 mode (3 e1 into ds2). 7210 0 0 0 0 0lpc(1:0)e1
peb 3445 e register description data sheet 115 2001-06-29 d2tcom ds2 transmit command register access : read/write address : 32 h reset value : 00 h iais insert ds1/e1 ais setting iais(x) enables transmission of the alarm indication signal in tributary x of the ds2 signal. ais is an all ?1? signal. 0 normal operation. 1 insert ais in low speed tributary x. finsc fault insertion code this bit enables transmission of faults for testing purposes. 0 no fault insertion. 1 insert f-bit errors at low rate (2 out of 5 f-bits). 2 insert f-bit errors at high rate (2 out of 4 f-bits). 3 insert m-bit framing bit error (ds1 mode) or p-bit error (itu-t g.747) sra set remote alarm this bit enables transmission of the ds3 remote alarm. in ds1 modes remote alarm is transmitted in subframe 4, block 1 overhead bit and in itu-t g.747 remote alarm is transmitted in bit 2 of ?set ii?. 0 normal operation. 1 enable transmission of remote alarm. res itu-t g.747 reserved bit this bit sets the value to be transmitted in the reserved bit of itu-t g.747 format. 0 transmit reserved bit as ?0?. 1 transmit reserved bit as ?1?. 7 43210 iais(3:0) finsc(1:0) sra res
peb 3445 e register description data sheet 116 2001-06-29 d2tlpc ds2 transmit ds1/e1 remote loopback/loopback code insertion register access : read/write address : 33 h reset value : 00 h r2t ds2 tributary receive to transmit loop (remote loop) setting bit r2t(x) enables the remote loop for tributary x where the incoming tributary x is mirrored to the ds2 transmitter. 0 disable remote loop. 1 enable remote loop. lpc send loopback code for tributary n setting lpc(x) enables transmission of the loopback code in tributary x. the loopback code inserted is specified in d2tcfg.lpc. 0 disable transmission of loopback code. 1 enable transmission of loopback code. 7430 r2t(3:0) lpc(3:0)
peb 3445 e register description data sheet 117 2001-06-29 d2ttm0, d2ttm1, d2ttm2, d2ttm3 ds2 transmit tributary map register access : read/write address : 34 h , 35 h , 36 h , 37 h reset value : 00 h tn tributary number a (transmit) tributary map register specifies the data and clock source for the seven m12 multiplexers and the four internal spare links (please refer to section ?tributary mapper? on page 37 for a detailed description of the tributary mapper). the m12 multiplexer to be programmed is selected via d2tsel.gn. where gn can be in the range of 0..6. to program the four internal spare links gn must be set to 7. now each of the four inputs of the selected m12 multiplexer (or the four spare links) can be programmed by the four tributary map registers d2ttm0..3 (d2ttm0 programs the first input, .., d2ttm3 programs the fourth input). this process maps any of the incoming 32 inputs to the selected input of the m12 multiplexer. after reset interfaces 1..32 are mapped to tributaries 1..32. example (please refer to figure 7 on page 37): the interface 14 (ttc(14), ttd(14)) shall be connected to tributary 7 (the third input of the second m12 multiplexer). 1. write 01 h to d2tsel.gn. this command selects the second m12 multiplexer (gn counts from 0..7). 2. write 0d h (= 13 d ) to d2ttm2.tn. this command assigns interface 14 (tn counts from 0..31) to the third input of the second m12 multiplexer. 74 0 0 0 0tn(4:0)
peb 3445 e register description data sheet 118 2001-06-29 d2rsel ds2 receive group select register access : read/write address : 40 h reset value : 00 h note: this register is an indirect access register, which must be programmed before accessing the register ds2 transmit registers. gn group number this bit field selects the ds2 group number, which can be accessed via the ds2 receive registers. please refer to section ?tributary mapper? on page 37 for a detailed description of the tributary mapper and to page 124 for programming examples. 0..7 group number. 720 0 0 0 0 0gn(2:0)
peb 3445 e register description data sheet 119 2001-06-29 d2rcfg ds2 receive configuration register access : read/write address : 41 h reset value : 00 h note: itu-t g.747 mapping and loop back codes are controlled by bits e1 and lpc in the ds3 transmit configuration register d2tcfg. ds1/e1 and loopback codes are controlled by e1 and lpc fields of the d2tcfg register. ecm error counter mode ds2 errors are counted in background and copied to foreground (error counter registers) when condition selected via ecm is met. 0 counter values are copied to foreground when copy command is executed. see also register ds3com. 1 the counter values are copied to the foreground register in one second intervals. at the same time the background registers are reset to zero. this operation is synchronous with the periodic one second interrupt which alerts software to read the register. aais automatic ais insertion this bit enables automatic insertion of ais in downstream direction if ds2 framer or ds3 framer is out of frame. 0 disable automatic insertion of ais. 1 enable automatic insertion of ais. mfm multiframe framing mode this bit selects the m-bit error condition which triggers the ds2 framer to start a new frame search. it is valid in ds1 mode only. 0 f-frame search started if 3 contiguous multiframes have m-bit errors. 1 inhibit new f-frame search due to m-bit errors. 73210 0 0 0 0 ecm aais mfm ffm
peb 3445 e register description data sheet 120 2001-06-29 ffm f-framing mode this bit selects the f-bit error condition which triggers the ds2 framer to start a new frame search. 0 a new frame search is started when 2 out of 4 contiguous f-bits are in error. 1 a new frame search is started when 2 out of 5 contiguous f-bits are in error.
peb 3445 e register description data sheet 121 2001-06-29 d2rcom ds2 receive command register access : read/write address : 42 h reset value : 00 h esimc error simulation code this bit field enables error simulation. during error simulation the device generates error interrupts and error status messages. nevertheless the service is not affected. 0 normal operation (no error simulation) 1 simulate 2 receive f-bit errors/multiframe (186 sec) 2 simulate 2 receive m-bit errors/multiframe (186 sec) (ds-1 mode) receive parity error/multiframe (133 sec) (itu-t g.747 mode) 3 simulate remote alarm 4 simulate loss of frame (red alarm timer) note:this simulation is service affecting if automatic ais insertion is enabled. 5 simulate ais (ais alarm timer) 6 simulate receive loop command c2nc copy ds2 error counters only valid when d2rcfg.ecm is set to ?0?. values of ds2 background registers are copied to foreground. background registers are not cleared. command is self clearing and completes before next register access is possible i.e. software can write command and then immediately read the counters without starting a delay timer. 0 no operation. 1 copy background counters to foreground. 76 4 10 0 esimc(2:0) 0 0c2ncc2c
peb 3445 e register description data sheet 122 2001-06-29 c2c copy and clear ds2 error counters only valid when d2rcfg.ecm is set to ?0?. values of ds2 background registers are copied to foreground. background registers are cleared. command is self clearing and completes before next register access is possible i.e. software can write command and then immediately read the counters without starting a delay timer. 0 no operation. 1 copy background counters to foreground. clear background counters.
peb 3445 e register description data sheet 123 2001-06-29 d2rimsk ds2 receive interrupt mask register access : read/write address : 43 h reset value : 3f h this register provides the interrupt mask for ds2 status interrupts and ds2 loopback code interrupts. see register d2rstat and d2rlpcs for interrupt conditions. the following definition applies: 1 the corresponding interrupt vector will not be generated by the device. 0 the corresponding interrupt vector will be generated. lpcs mask ?loopback code status? (flagged in d2rlpcs) ais mask ?ais alarm state? reds mask ?red alarm state? res mask ?reserved bit? ras mask ?ds2 remote alarm state? fas mask ?ds2 frame alignment state? 7 543210 0 0 lpcd aiss reds res ras fas
peb 3445 e register description data sheet 124 2001-06-29 d2rtm0, d2rtm1, d2rtm2, d2rtm3 ds2 receive tributary map register access : read/write address : 44 h , 45 h ,46 h , 47 h reset value : 00 h tn tributary number a (receive) tributary map register specifies the data and clock source for one of the 32 ds1/e1 outputs (please refer to section ?tributary mapper? on page 37 for a detailed description of the tributary mapper). the outputs are divided into eight groups where each group represents four consecutive output ports, i.e. 1..4, 5..8, .. , 29..32. the group to be programmed is selected via d2rsel.gn. now each of the four outputs of the selected group can be programmed by the four tributary map registers d2rtm0..3. this process maps any of the incoming 28 tributaries of the ds3 signal or any of the four internal spare links to an output. after reset interfaces 1..32 are mapped to tributaries 1..32. example (please refer to figure 7 on page 37): the interface 22 (rtc(22), rtd(22)) shall be connected to the tributary 7 (the third output of the second m12 demultiplexer). 1. write 05 h to d2rsel.gn. this command selects the output group 5 consisting of the output pins 21..24 and in this case the registers d2rtm0..d2rtm3 represent the output pins 21..24. 2. write 06 h to d2rtm1.tn. this command assigns tributary seven (tn counts from 0..31) to output 22. 74 0 0 0 0tn(4:0)
peb 3445 e register description data sheet 125 2001-06-29 d2rlais ds2 receive local ds1/e1 loopback/ais insertion register access : read address : 48 h reset value : 00 h iais insert ais setting bit x of bit field iais(x) enables insertion of ais in tributary x of the demultiplexed ds2 signal in downstream direction. 0 no function. 1 enable insertion of ais in tributary x of demultiplexed ds2 tributary. t2r enable loopback setting bit x of bit field t2r enables loopback from transmit to receive of tributary x (local loop of ds1/e1 tributary). 0 no loopback. 1 enable loopback from transmit to receive. 7430 iais(3:0) t2r(3:0)
peb 3445 e register description data sheet 126 2001-06-29 d2rstat ds2 receive status register access : read address : 49 h reset value : 00 h each bit in the ds2 framer receive status register declares a specific condition dependent on the selected modes. the following convention applies to the individual bits: 0 the named status is not or no longer existing. 1 the named status is currently effective. except for cofa every bit can be used to generate an interrupt. interrupts can be masked in register d2rimsk. aiss ds2 ais alarm state (unframed all ?1?s pattern) ais is considered valid in a multiframe when fewer than 5 zeros are detected. at 10 -3 error rates, 1 zero per multiframe is typical. a valid ds2 signal without any bit errors has at least 5 zeros. the ais flag nominally changes when the ais condition is persistent as per alarm timing parameters defined in register d2rap. the exact time necessary to change the flag could be greater in extremely high error rates. the ais state is integrated by incrementing or decrementing a counter at the end of each multiframe depending on the ais condition being valid or invalid respectively. reds ds2 red alarm state (loss of frame alignment). the red alarm flag nominally changes when loss of frame alignment condition is persistent as per alarm timing parameters defined in register d2rap. the exact time necessary to change the flag could be greater if the fas flag is not constant because the frame alignment state is integrated by incrementing or decrementing a counter at the end of each multiframe when the fas flag set or cleared respectively. note that the 7 543210 0 0 aiss reds res ras cofa fas
peb 3445 e register description data sheet 127 2001-06-29 framer?s verification algorithm is designed to prevent a bouncing fas flag. res reserved bit this bit indicates the status of bit 3 in set ii of itu-t g.747 mode. is it updated if the ds2 framer is aligned and when its state persists for at least 8 multiframes. ras ds2 remote alarm state this bit indicates that remote alarm is active. changes are reported when they persist for 3 multiframes. in ds1 mode changes on m x bit are reported, in itu-t g.747 mode changes of bit 1 of set ii are reported. cofa change of frame alignment this bit indicates a change of frame alignment event. it is set when the ds2 framer found a new frame alignment and when the new frame position differs from the expected frame position. fas ds2 frame alignment state this bit indicates that the ds2 framer is not aligned.
peb 3445 e register description data sheet 128 2001-06-29 d2rlpcs ds2 receive loopback code status register access : read address : 4a h reset value : 00 h lpcd(n) loopback command detected lpcd(x) indicates that a loopback request was received. a loopback request for tributary x is indicated by inverting one of the 3 c-bits of the x th subframe. the c-bit is determined by d2tcfg.lpc. a command state change must persist for 5 contiguous multiframes before it will be reported. 0 no loopback code being received. 1 loopback code being received. 730 0 0 0 0 lpcd(3:0)
peb 3445 e register description data sheet 129 2001-06-29 d2rap ds2 receive alarm timer parameters access : read/write address : 4b h reset value : 00 h ais ais criteria this bits sets the error rate for ais detection. declaration of ais is specified by bits cm and cv. itu-t g.747: 0 ais condition is recognized when the alarm indication signal is received with less than 5 errors in each of 2 consecutive multiframes. 1 ais condition is recognized when the alarm indication signal is received with less than 9 errors in each of 2 consecutive multiframes. m12 format: 0 ais condition is recognized when the alarm indication signal is received with less than 3 errors in 3156 bits. 1 ais condition is recognized when the alarm indication signal is received with less than 9 errors in 3156 bits. cm counter mode this bit selects the alarm timer mode. if counter mode is set to multiframes (?0?) the value in cv determines the number of multiframes after which the TE3-MUX declares ais or red. when counter mode is set to ?? milliseconds? (?1?) the value in cv determines the time in cv x 0.5 ms after which ais or red is declared. 0 multiframes. 1 ? milliseconds. 765 0 ais cm cv(5:0)
peb 3445 e register description data sheet 130 2001-06-29 cv counter value dependent on bit cm the counter value specifies the number of frames or the time in multiples of 0.5 milliseconds when ais or red is declared, i.e. setting cv to 20 and cm to ?1? sets the alarm integration time to 10 milliseconds. 0..63 counter value.
peb 3445 e register description data sheet 131 2001-06-29 d2rfec ds2 receive framing bit error counters access : read/write address : 4c h reset value : 0000 h fe(15:0) framing bit errors error counter mode (clear on read or errored second) depends on register d2rcfg.ecm. for ds1 mode framing bit errors include f-bit and m-bit errors. for g747 mode, individual bits in the frame alignment signal (fas) are counted. errors are not counted in out of frame state. d2rpec ds2 receive parity bit error counter access : read/write address : 4e h reset value : 0000 h pe(15:0) parity errors in itu-t g.747 mode error counter mode (clear on read or errored second) depends on register d2rcfg.ecm. errors are not counted in out of frame state. 15 0 fe(15:0) 15 0 pe(15:0)
peb 3445 e register description data sheet 132 2001-06-29 7.2.3 test unit registers tutcfg test unit transmit configuration register access : read/write address : 50 h reset value : 0000 h inv invert output this bit enables inversion of the test unit output. bit inversion is done after the zero suppression insertion point. 0 no inversion 1 invert pattern generator output fbt feedback tap this bit field sets the feedback tap in pseudorandom pattern mode. prbs shift register input bit 0 is xor of shift register bits len and fbt. len pattern generator length this bit field sets the pattern generator length to 1..32. zs enable zero suppression this bit enables zero suppression where a ?1? bit is inserted at the output if the next 14 bits in the shift register are ?0?. 0 no zero suppression 1 zero suppression. md generator mode this bit selects the generator mode of the test unit to be either prbs or fixed pattern mode. 0 pseudorandom pattern (prbs) 1 fixed pattern 15 13 12 8 6 2 1 0 0 0 inv fbt(4:0) 0len(4:0)zsmd
peb 3445 e register description data sheet 133 2001-06-29 tutcom test unit transmit command register access : write address : 52 h reset value : 00 h note: all commands are self clearing i.e. user does not have to clear command. the maximum command rate is limited by clock rate of unit under test and the associated synchronization process. write interval should be > 4 transmit clock periods e.g. 2.6 s for ds1 tributary test or 634 ns for t2 tributary test. lder load error rate register this bit loads the value of the error rate register tuteir to the test unit transmitter. the command can be given while the transmitter is running. 0 no function. 1 copy value of register tuteir to transmit clock region. in1e insert one error in output this bit enables a single error insertion in the next bit after command was written. 0 no function 1 single error insertion. stop stop pattern generation. this bit stops the test unit transmitter. when stopped output becomes all ?1?. 0 no function. 1 stop pattern generation. 73210 0 0 0 0lderin1estopstrt
peb 3445 e register description data sheet 134 2001-06-29 strt start transmitter. this bit starts the test unit transmitter with the parameters defined in register tutcfg. in fixed pattern mode the pattern needs to be programmed via register tutfp0/1 prior to starting the transmitter. 0 no operation. 1 start test unit.
peb 3445 e register description data sheet 135 2001-06-29 tuteir test unit transmit error insertion rate register access : read/write address : 53 h reset value : 00 h mtst manufacturing test. must be written to ?0? for normal operation. txer transmit error insertion rate. this bit field determines the error insertion rate of the test unit transmitter. 000 no errors 001 10 -1 (1 in 10) 010 10 -2 (1 in 100) 011 10 -3 (1 in 1 000) 100 10 -4 (1 in 10 000) 101 10 -5 (1 in 100 000) 110 10 -6 (1 in 1 000 000) 111 10 -7 (1 in 10 000 000) 7320 0 0 0 0 mtst txer(2:0)
peb 3445 e register description data sheet 136 2001-06-29 tutfp0 test unit transmit fixed pattern low word access : read/write address : 54 h reset value : 0000 h fp fixed pattern low word see description below. tutfp1 test unit transmit fixed pattern high word access : read/write address : 56 h reset value : 0000 h fp fixed pattern high word the 32 bit fixed pattern is distributed over two 16 bit registers and contains the pattern which is transmitted repetitively from bit fp(tutcfg.len) down to fp(0) when test unit is operated in fixed pattern generator mode. 15 0 fp(15:0) 15 0 fp(31:15)
peb 3445 e register description data sheet 137 2001-06-29 turcfg test unit receive configuration register access : read/write address : 58 h reset value : 0000 h aim auxiliary interrupt mode this bit field enables the auxiliary interrupt mask aim of register turimsk. in normal operation and if not masked every status event generates an interrupt event. in auxiliary interrupt mode an individual status event generates one interrupt event and further status events of the same class, i.e. ?bit error detected?, are masked via an internal mask. this prevents excessive interrupt floods. see register turimsk for further details. 0 normal operation 1 auxiliary interrupt mode das disable automatic synchronization this bit disables automatic resynchronization in case of high bit error rates. if automatic resynchronization is enables the receiver automatically tries to resynchronize to the received test pattern. 0 enable automatic resynchronization. 1 disable automatic resynchronization. fbt feedback tap this bit field sets the feedback tap of the test unit synchronizer (receiver) in pseudorandom pattern mode. next input to prbs reference shift register (bit 0) is xor of shift register bits len and fbt. len reference shift register length this bit field sets the length of the receiver?s test pattern register. 15 13 12 8 6 2 1 0 aim 0 das fbt(4:0) 0len(4:0)zsmd
peb 3445 e register description data sheet 138 2001-06-29 zs enable zero suppression this bit enables zero suppression at the test unit receiver. a ?1? is expected and inserted at the input if the next 14 bits in the shift register are set to ?0?. 0 no zero suppression. 1 enable zero suppression. md generator mode this bit sets the generator mode of the test unit to either prbs or fixed pattern. 0 pseudorandom pattern (prbs) 1 fixed pattern
peb 3445 e register description data sheet 139 2001-06-29 turcom test unit receive command register access : write address : 5a h reset value : 00 h note: all commands are self clearing i.e. user does not have to clear command. the maximum command rate is limited by clock rate of unit under test and the associated synchronization process. write interval should be > 4 transmit clock periods e.g. 2.6 s for ds1 tributary test or 634 ns for t2 tributary test. frs force resynchronization. this bit forces the receiver to resynchronize to the received bit stream. only applicable if turcfg.das = ?1?. 0 no function. 1 force resynchronization of receiver. rdf copy receiver?s 32 bit pattern this bit loads the test units internal receiver pattern to register turfp in fixed pattern mode. in synchronous state turfp will be loaded with the pattern received. in asynchronous state turfp with a 32-bit sample of the last received bit stream. 0 no function. 1 update register turfp with synchronizer pattern. rdc copy bit counter and error counter this bit loads the test units internal bit counter and error counter to registers turbc0,1 and turec0,1. afterwards the bit counter and the error counter is cleared. 0 no function. 1 copy counter. 7 543210 0 0 frs rdf rdc caim stop strt
peb 3445 e register description data sheet 140 2001-06-29 caim clear auxiliary interrupt masks. this bit resets the internal auxiliary mask. see turcfg.aim. 0 no operation 1 clear auxiliary interrupts stop stop receiver setting this bit stopes the test unit receiver. strt start receiver. this bit loads and starts the test unit receiver with the parameters defined in register turcfg. 0 no operation. 1 load/start test unit receiver.
peb 3445 e register description data sheet 141 2001-06-29 turermi test unit receive error measurement interval register access : read/write address : 5b h reset value : 00 h tst test mode this bit enables test of the measurement interval timer. 0 normal operation 1 auto test of measurement interval function. end of measurement interrupt should be asserted after approximately 4250 receive clock cycles (if enabled). the lower three bits of register fpat should be ?111?. rxmi receive error rate measurement interval this bit field defines the measurement interval in terms of input bits for measurement of receive bit error rate. at the end of the measurement window, contents of background error counter are automatically copied to foreground error counter and reset for next measurement interval. an interrupt can be generated at the end of each measurement interval. 000 b max measurement interval of 2 32 -1 001 b 10 3 bits 010 b 10 4 bits 011 b 10 5 bits 100 b 10 6 bits 101 b 10 7 bits 110 b 10 8 bits 111 b 10 9 bits 7320 0 0 0 0tst rxmi(2:0)
peb 3445 e register description data sheet 142 2001-06-29 turimsk test unit receive interrupt mask register access : read/write address : 5c h reset value : 1f1f h this register provides the interrupt mask for test unit interrupts. see register turstat. the following definition applies: 1 the corresponding interrupt vector will not be generated by the device. 0 the corresponding interrupt vector will be generated. erxm mask ?end of receive error rate measurement? bed mask ?bit error detected? all1 mask ?all ?1? pattern received? los mask ?loss of signal? syn mask ?change in receiver synchronization state? aim flags have same layout as the above five mask but are internal masks that are set automatically following the interrupt in the aim mode. this mask prevents excessive bus load in error conditions. aim flags are cleared by the turcom.caim command. they are ?read only? flags in this register. 15 12 8 43210 0 0 0 aim(4:0) 0 0 0 erxm bed all1 los syn
peb 3445 e register description data sheet 143 2001-06-29 turstat test unit receive status register access : read address : 5e h reset value : 0001 h inv inverted pattern this bit indicates that the received prbs sequence is inverted. 0 not inverted. 1 inverted. la1 latched ?input all ?1?? this bit indicates that the condition ?input all ?1?? was active since last status register read. la0 latched ?input all ?0?? this bit indicates that the condition ?input all ?0?? was active since last status register read. loos latched out of synchronization. this bit indicates that the receiver was out of synchronization since last status register read. emi end of measurement interval this bit indicates that the end of the measurement internal was reached since last read of error counter or that command turcmd.rdc was given. the results of the bit error rate test are available in register turbc0,1 and turec0,1. this flag is cleared when the error counter is read. counters will not be overwritten while emi is ?1?. lbe latched bit error detected flag. this bit indicates that at least ?1? one bit error occurred since last read of this register. it is cleared by status register read. a1 input all ?1?s this bit indicates that the input contained all ?1? during the last 32 bits. it is reset if at least one ?0? occurs in 32 bits. 15 876543210 0 0 0 0 0 0 0invsla1la0loosemilbea1 a0oos
peb 3445 e register description data sheet 144 2001-06-29 a0 input all ?0?s this bit indicates that the input contained all ?0? during the last 32 bits. it is reset if at least one ?1? occurs in 32 bits. oos receiver out of synchronization this bit indicates the status of the test unit synchronizer.
peb 3445 e register description data sheet 145 2001-06-29 turbc0 test unit receive bit counter low word access : read address : 60 h reset value : 0000 h bc(31:0) bit counter see description below. turbc1 test unit receive bit counter high word access : read address : 62 h reset value : 0000 h bc(31:0) bit counter bc is a 32 bit counter which is split between two 16 bits registers. it counts receive clock slots when the receiver is enabled. bits are counted in a background register which is not directly readable. the values are transferred to the two 16 bit foreground (readable) registers and cleared in one of the two ways: 1. assert command turcom.rdc. 2. automatically at end of measurement interval. the background register is transferred to the foreground register and cleared in the same way as the bit error counter (see previous section). 15 0 bc(15:0) 15 0 bc(31:16)
peb 3445 e register description data sheet 146 2001-06-29 when the error registers are read in response to the ?end of measurement interval? interrupt vector, reading this register is not necessary because the measurement interval would be known. however the user could assert command turcom.rdc to terminate the measurement interval early and transfer the current bit error count and bit count to the foreground registers (polling mode).
peb 3445 e register description data sheet 147 2001-06-29 turec0 test unit receive error counter low word access : read address : 64 h reset value : 0000 h ec(31:0) error counter see description below. turec1 test unit receive error counter high word access : read address : 66 h reset value : 0000 h ec(31:0) error counter this 32 bit counter counts receive errors detected when receiver is enabled and in synchronized state. when the ?bit error detected? interrupt is enabled, it will be asserted and then automatically masked when this counter is incremented. errors are counted in a background register (not directly readable) until: 1. the user asserts command turcom.rdc. 2. the end of measurement interval is reached and the last result was read. in both cases the value of the background register is copied to turec.ec and the measured values are accessible. an ?end of 15 0 ec(15:0) 15 0 ec(31:16)
peb 3445 e register description data sheet 148 2001-06-29 receive error rate measurement? interrupt vector is optionally generated.
peb 3445 e register description data sheet 149 2001-06-29 turfp0 test unit receive fixed pattern low word access : read address : 68 h reset value : 0000 h fp(31:0) fixed pattern see description below. turfp1 test unit receive fixed pattern high word access : read address : 6a h reset value : 0000 h fp(31:0) fixed pattern this 32 bit field is distributed over two 16 bit registers and is used in the fixed pattern mode (turcfg.md=?1?). the turcom.rdf command will copy the current state of the receiver?s 32 bit pattern generator to this register. if the receiver is synchronized, bits fp(turcfg.len:0) contain the fixed pattern being received. bit 0 is the most recently received. if not synchronized, the register contains a 32 bit sample of input data. 15 0 fp(15:0) 15 0 fp(31:16)
peb 3445 e register description data sheet 150 2001-06-29 7.2.4 test unit framer registers tutfcfg test unit transmit framer configuration register access : read/write address : 70 h reset value : 00 h om overwrite mode this bit enables test pattern overwrite mode. while in overwrite mode the generated prbs sequence will be overwritten by the frame bits. when overwrite is disabled the generated prbs sequence is placed into the payload field of the ds1/e1 signal. 0 disable overwrite mode. 1 enable overwrite mode. sraf select remote (yellow) alarm format setting this bit enables the remote alarm format in ds1 mode. this bit has no function in e1 mode. ds1: f12 0 bit 2 = 0 in every channel. 1 fs bit of frame 12. fm framer mode this bit selects the frame format of ds1 or e1 mode. ds1 0 select esf (f24) format. 1 select sf (f12) format. e1 0 select double frame format. 1 select multiframe format. 7 43210 0 0 0omsraffmt1e1ef
peb 3445 e register description data sheet 151 2001-06-29 t1e1 select ds1/e1 mode this bit switches between ds1 and e1 mode. 0 select ds1 mode. 1 select e1 mode. ef enable framer this bit enables the framer for framed ds1/e1 error insertion mode. 0 disable framer. (unframed bit error rate test) 1 enable framer. (framed bit error rate test)
peb 3445 e register description data sheet 152 2001-06-29 tutfcom test unit transmit framer command register access : read/write address : 71 h reset value : 00 h ebit set active e-bit (e1 mode) this bit inserts an active e-bit. ebit is self clearing. 0 normal operation. 1 set active e-bit. crc insert crc error this bit enables insertion of crc error. crc is self clearing. 0 normal operation. 1 insert crc error. fe insert frame error this bit enables insertion of framing errors. fe is self clearing. 0 normal operation. 1 insert frame error. ra send remote alarm this bit enables insertion of remote alarm. 0 disable remote alarm. 1 send remote alarm. 73210 0 0 0 0 ebit crc fe ra
peb 3445 e register description data sheet 153 2001-06-29 turfcfg test unit receive framer configuration register access : read/write address : 74 h reset value : 00 h om overwrite mode this bit enables test pattern overwrite. in overwrite mode the test unit discards the generated bits while the f-bit (ds1 mode) respectively time slot 0 (e1 mode) is received. when overwrite mode is disabled the complete test pattern is expected in the payload of the frame. 0 disable overwrite mode. 1 enable overwrite mode. rram receive remote alarm mode the condition for remote (yellow) alarm detection in ds1-sf mode can be selected via this bit. remote alarm detection is flagged in register turfstat.rra. 0 detection: bit 2 = ?0? in every speech channel per frame. release: the alarm will be reset when above conditions are no longer detected. 1 detection: fs-bit of frame 12 is forced to ?1?. release: the alarm will be reset when above conditions are no longer detected. 7 43210 0 0 0 om rram fm t1e1 ef
peb 3445 e register description data sheet 154 2001-06-29 fm framer mode this bit selects the frame format of ds1 or e1 mode. ds1 0 select esf (f24) format. 1 select sf (f12) format. e1 0 select double frame format. 1 select multiframe format. t1e1 select ds1/e1 mode this bit switches between ds1 and e1 mode. 0 select ds1 mode. 1 select e1 mode. ef enable framer this bit enables the framer for framed ds1/e1 error detection mode. 0 disable framer. (unframed ds1/e1 bit error rate test) 1 enable framer. (framed ds1/e1 bit error rate test)
peb 3445 e register description data sheet 155 2001-06-29 turfcom test unit receive framer command register access : read/write address : 75 h reset value : 00 h cc copy and clear framer error counters values of framer background registers are copied to foreground. background registers are cleared. command is self clearing and completes before next register access is possible i.e. software can write command and then immediately read the counters without starting a delay timer. 0 no operation. 1 copy background counters to foreground. clear background counters. 70 0 0 0 0 0 0 0cc
peb 3445 e register description data sheet 156 2001-06-29 turfstat test unit receive framer status register access : read address : 76 h reset value : 00 h rra received remote alarm (yellow alarm) condition for receive remote alarm is defined by bit turfcfg.rram. the flag is set after detecting remote alarm (yellow alarm). lfa loss of frame alignment this bit reports loss of frame alignment. in ds1 mode loss of frame alignment is reported when 2 out of 4 framing bit errors are detected. 710 0 0 0 0 0 0 rra lfa
peb 3445 e register description data sheet 157 2001-06-29 turffec test unit receive framing error counter access : read address : 78 h reset value : 00 h fe framing error counter the counter will not be incremented during asynchronous state. the error counter is cleared on read. ds1: f12 the counter will be incremented when incorrect ft and fs bits are received. ds1: esf the counter will be incremented when incorrect fas bits are received. e1 the counter will be incremented when incorrect fas words are received. 15 0 fe(15:0)
peb 3445 e register description data sheet 158 2001-06-29 turfcec test unit receive framer crc error counter access : read address : 7a h reset value : 00 h cr crc errors the counter will not be incremented during asynchronous state. the error counter is cleared on read. ds1: f12 no function. ds1: esf the counter will be incremented when a multiframe has been received with a crc error. e1: doubleframe no function. e1: crc-4 multiframe in crc-4 multiframe mode the counter will be incremented when a submultiframe has been received with a crc error. 15 0 cr(15:0)
peb 3445 e register description data sheet 159 2001-06-29 turfebc test unit receive framer errored block counter access : read address : 7c h reset value : 00 h eb e-bit counter the counter will not be incremented during asynchronous state. the error counter is cleared on read. ds1 no function. e1: doubleframe no function. e1: crc-4 multiframe the counter will be incremented each time the framer receives a crc-4 multiframe with s i bit in frame 13 or frame 15 set to zero. 15 0 eb(15:0)
peb 3445 e register description data sheet 160 2001-06-29 7.2.5 far end alarm and control channel (bom) registers frcfg feac receive configuration register access : read/write address : 80 h reset value : 0000 h rtf rfifo threshold level this bit field sets the threshold of the receive fifo and is applied to both pages of the receive fifo. a ?receive pool full? interrupt vector will be generated, when the programmed threshold is reached. the threshold value is given as follows: 00 b 32 byte threshold 01 b 16 byte threshold 10 b 4 byte threshold 11 b 2 byte threshold bfe enable bom filter mode this bit selects, that byte oriented messages have to be filtered. the bom is reported only if 7 out 10 data is received. 0 disable bom filter mode. 1 enable bom filter mode. brm bom receive mode this bit switches between continuous and 10 byte packet reception of the receive signalling controller. in 10 byte packet mode a receive fifo full interrupt is generated after 10 bytes. in continuous reception mode a receive message interrupt is generated when the receive fifo threshold level is reached. 0 enable 10 byte packets. 1 enable continuous reception. 15 76 210 0 0 0 0 0 0 0 0rtf(1:0) 0 0 0bfebrmron
peb 3445 e register description data sheet 161 2001-06-29 ron receiver on/off this bit switches the receiver of the far end alarm and control channel to operational (on) or inoperational state (off). it is recommended to issue a ?receive message complete? command after the receiver was initialized (fhnd.rmc = ?1?) in order to clear arbitrary receive fifo contents. 0 switch receiver off. 1 switch receiver on.
peb 3445 e register description data sheet 162 2001-06-29 frff feac receive fifo register access : read address : 82 h reset value : 0000 h rfifo receive fifo data this bit field contains the first 16 bit word of the receive fifo of the signalling controller. the receive fifo itself consists of two pages with 32 bytes. one page is always used in background and is not visible to the microprocessor. the microprocessor sees one fifo of 32 bytes only. thus a maximum of 16 words is stored inside the receive fifo at a time. data stored in the receive fifo can be read in 8- or 16-bit accesses. nevertheless if the port status register indicates an odd byte count the higher byte of the last word is not valid. port status and fifo operations can be accessed via register fpsr and register fhnd. the first bit received is stored in bit 0. 15 7 0 rfifo(15:0) 0 0 0 0 0 0 0 0rfifo(7:0)
peb 3445 e register description data sheet 163 2001-06-29 fxcfg feac transmit configuration register access : read/write address : 84 h reset value : 00 h xon transmitter on/off this bit switches the transmitter of the facility data link to operational (on) or inoperational state (off). 0 switch transmitter off. 1 switch transmitter on. 70 0 0 0 0 0 0 0xon
peb 3445 e register description data sheet 164 2001-06-29 fxff feac transmit fifo access : write address : 86 h reset value : 0000 h xfifo transmit fifo data this bit field contains the first 16 bit word of the transmit fifo of the signalling controller. the transmit fifo itself consists of two pages with 32 bytes. one page is always used in background and is not visible to the microprocessor. the microprocessor sees one fifo of 32 bytes only. thus a maximum of 16 words can be stored inside the transmit fifo at a time. data stored in the transmit fifo can be written in 8- or 16-bit accesses. nevertheless if the user wants to transfer an odd number of bytes the last access to the transmit fifo register must be a byte access. port status and fifo operations can be accessed via register fpsr and register fhnd. data written to the transmit fifo is sent starting with bit 0 up to bit 15. note: the feac transmitter does not automatically insert ?ff? between message bytes. the ?ff? bytes have to be provided as part of the message to be transmitted. thus messages stored in the transmit fifo must have the following structure: 11111111 b 0xxxxxx0 b . no te: if the transmit fifo is not completely filled (32 bytes stored in the fifo page) the transmitter may insert gaps between the packet stored in the current fifo page and the packet stored in the following fifo page. thus in order to sent bom sequences longer than 32 bytes the transmit fifo has to filled in blocks of 32 bytes except for the last part of the sequence which may not completely occupy a fifo page. 15 7 0 xfifo(15:0) 0 0 0 0 0 0 0 0xfifo(7:0)
peb 3445 e register description data sheet 165 2001-06-29 fpsr feac port status register access : read address : 88 h reset value : 2000 h xra transmit repeat active this bit indicates that the transmit signalling controller is operating in repeat mode. 0 normal operation 1 repeat operation xfw transmit fifo write enable this bit indicates that data can be written to xff.xfifo. this bit is for polling use with the same meaning as the ?transmit pool ready? interrupt vector. rbc receive byte count this bit field indicates the amount of data stored in the receive fifo. valid after a ?receive message end? interrupt vector is generated. receive byte count will be cleared, when a ?receive message clear? command is executed via register hnd. note: a zero byte count in combination with a ?receive pool full? or ?receive message end? interrupt vector means that 32 bytes are available in the receive fifo. however evaluating rbc is not necessary when the ?receive pool full? interrupt was received. brfo bom receive fifo overflow 0 no overflow 1 rff overflow the status word will be cleared after a ?receive message clear? command is issued. 15 14 13 12 8 5 4 0 0 xra xfw rbc(4:0) - - brfo stat(4:0)
peb 3445 e register description data sheet 166 2001-06-29 stat receive fifo status this bit field reports the status of the data stored in the receive fifo. 00000 b bom filtered data declared this status is reported when ?bom filtered data? is enabled, and 7 out of 10 bom data are received (see also register bit frcfg.bfe). 00001 b bom data available bom data received is continuously written to the receive fifo. if '10 byte packet mode' is enabled then this status byte is sent after 10 bytes are written into fifo. otherwise, whenever the receive fifo is full, this status byte is generated. 00010 b bom 7e this status reported when the hdlc flag 7e h was detected. 00011 b bom filtered data undeclared this is sent only if 'bom filtered mode' is enabled. this is sent whenever 3 valid bom data is received but all these data is not same as the bom data for which the status 'bom filtered data declared' was sent earlier. basically, this means that 7 out of 10 condition is no longer valid. this status is useful, when bom data pattern changes from one valid pattern to another and bom filtered data is enabled. 00100 b bom idle this message is generated when the receiver was not able to detect a bom message in the last 32 bits, e.g. the idle pattern (all ?1?) was sent.
peb 3445 e register description data sheet 167 2001-06-29 fhnd feac handshake register access : write address : 8a h reset value : 0000 h note: receive command (bit 8) and transmit commands (bit 5 down to bit 0) can not be issued at the same time. doing so will cause the facility data link to omit the transmit commands. rmc receive message complete this bit is a confirmation from cpu that a data block has been read from rfifo following a ?receive pool full? or ?receive message end? interrupt vector and that the occupied page can now be released. note: if this bit is set, the low byte (transmit commands) of the register hnd is ignored. 0 no function 1 release page of receive fifo. xres transmitter reset this bit resets the signalling controller transmit. however, the contents of the control register will not be reset. 0 normal operation 1 transmitter reset xrep transmission repeat setting this bit together with bit xtf indicates that the contents stored in xff.xfifo shall be repeatedly transmitted by the TE3-MUX. 0 no cyclic transmission. 1 enable cyclic transmission. xtf transmit transparent frame setting this bit indicates that the contents written to xff.xfifo shall be transmitted in transparent mode. 15 8 6 5 4 1 0 0 0 0 0 0 0 0rmc 0 0 xres xrep 0 0xtfxme
peb 3445 e register description data sheet 168 2001-06-29 0 no function 1 transmit data stored in xff.xfifo fully transparent, i.e. without bit stuffing and crc. xme transmit message end setting this bit indicates that the last data block written to xff.xfifo completes the current message.
peb 3445 e register description data sheet 169 2001-06-29 table 8 far end alarm and control transmit commands xres xrep xtf xme function 1--- reset port 0010 start transmission send fifo content in bom channel. 0011 stop transmssion stop transmission of fifo contents. transmission ends when content of transmit fifo has been sent completely. 0110 start transmission, enable automatic repetition send fifo content bom channel. automatically repeat transmission of fifo content. 0111 stop transmission, disable automatic repetition stop transmission after last byte stored in fifo has been sent. this command is issued when transmission started by command ? start transmission, enable automatic repetition ? shall be stopped.
peb 3445 e register description data sheet 170 2001-06-29 fmsk feac interrupt mask register access : read/write address : 8c h reset value : 00 h for each facility data link interrupt vector an interrupt vector generation mask is provided. generation of an interrupt vector itself does not necessarily result in assertion of the interrupt pin. for description of interrupt concept refer to section ?interrupt interface? on page 62 . the following definition applies: 1 the corresponding interrupt vector will not be generated by the device. 0 the corresponding interrupt vector will be generated. facility data link interrupt vector transmit alls mask ?all sent? xdu mask ??transmit data underrun? xpr mask ?transmit pool ready? facility data link interrupt vector receive rpf mask ?receive pool full? rme mask ?receive message end? rmi mask ?bom idle? 7 543210 0 0 alls xdu xpr rpf rme rmi
peb 3445 e register description data sheet 171 2001-06-29 7.2.6 c-bit path maintenance (hdlc) registers prcfg hdlc receive configuration register access : read/write address : 90 h reset value : 0000 h rmcp rmc polarity this bit sets the polarity of the rmc signal. 0 set polarity to active low. 1 set polarity to active high. drrp drr polarity this bit sets the polarity of the drr signal. 0 set polarity to active low. 1 set polarity to active high. dma activate dma this bit enables the dma functionality of the c-bit parity path maintenance data link receiver. while dma is active new data is indicated by an asserted drr signal. the end of a message is indicated by an asserted rmc signal. 0disable dma. 1 enable dma. rtf rfifo threshold level this bit field sets the threshold of the receive fifo and is applied to both pages of the receive fifo. a ?receive pool full? interrupt vector will be 15 109876 43210 0 0 0 0 0 rmcp drrp dma rtf(1:0) 0 inv riftf xcrc crc dis ron
peb 3445 e register description data sheet 172 2001-06-29 generated, when the programmed threshold is reached. the threshold value is given as follows: 00 b 32 byte threshold 01 b 16 byte threshold 10 b 4 byte threshold 11 b 2 byte threshold inv invert data input from receive framer this bit enables data inversion between receive framer and receive signalling controller. 0 disable data inversion. 1 enable data inversion. riftf report interframe time-fill change this bit selects, that interframe time-fill changes should be reported. 0 disable iff status messages. 1 enable iff status messages. xcrc transfer crc to rfifo this bit defines, that crc of incoming data packets shall be transferred to the receive fifo or not. 0 no transfer of crc to rfifo. 1 transfer of crc to rfifo. crcdis crc check disable this bit enables or disables the crc check of incoming data packets. 0 enable crc check. 1 disable crc check. ron receiver on/off this bit switches the receiver of the facility data link channel to operational (on) or inoperational state (off). it is recommended to issue a ?receive message complete? command after the receiver was initialized (phnd.rmc = ?1?) in order to clear arbitrary receive fifo contents. 0 switch receiver off. 1 switch receiver on.
peb 3445 e register description data sheet 173 2001-06-29 prff hdlc receive fifo register access : read address : 92 h reset value : 0000 h rfifo receive fifo data this bit field contains the first 16 bit word of the receive fifo of the signalling controller. the receive fifo itself consists of two pages with 32 bytes. one page is always used in background and is not visible to the microprocessor. the microprocessor sees one fifo of 32 bytes only. thus a maximum of 16 words is stored inside the receive fifo at a time. data stored in the receive fifo can be read in 8- or 16-bit accesses. nevertheless if the port status register indicates an odd byte count the higher byte of the last word is not valid. port status and fifo operations can be accessed via register ppsr and register phnd. the first bit received is stored in bit 0. 15 7 0 rfifo(15:0) 0 0 0 0 0 0 0 0rfifo(7:0)
peb 3445 e register description data sheet 174 2001-06-29 pxcfg hdlc transmit configuration register access : read/write address : 94 h reset value : 0000 h txmep txme polarity this bit sets the polarity of the txme signal. 0 set polarity to active low. 1 set polarity to active high. drtp drt polarity this bit sets the polarity of the drt signal. 0 set polarity to active low. 1 set polarity to active high. dma activate dma this bit enables the dma functionality of the c-bit parity path maintenance data link transmitter. while dma is active a data request is indicated by an asserted drt signal. the end of a message is indicated by the user with an asserted txme signal. 0disable dma. 1 enable dma. inv invert data this bit enables data inversion between transmit signalling controller and transmit framer. 0 disable data inversion. 1 enable data inversion. 15 10987 3210 0 0 0 0 0 txmep drtp dma 0 0 0 0inv dis crc sf xon
peb 3445 e register description data sheet 175 2001-06-29 discrc disable crc this bit enables crc generation and transmission on transmission of hdlc packets. 0 enable crc generation. 1 disable crc generation. sf shared flags this bit enables transmission of protocol data with shared flags. 0 disable shared flags. 1 enable shared flags. xon transmitter on/off this bit switches the transmitter of the facility data link to operational (on) or inoperational state (off). 0 switch transmitter off. 1 switch transmitter on.
peb 3445 e register description data sheet 176 2001-06-29 pxff hdlc transmit fifo register access : write address : 96 h reset value : 0000 h xfifo transmit fifo data this bit field contains the first 16 bit word of the transmit fifo of the signalling controller. the transmit fifo itself consists of two pages with 32 bytes. one page is always used in background and is not visible to the microprocessor. the microprocessor sees one fifo of 32 bytes only. thus a maximum of 16 words can be stored inside the transmit fifo at a time. data stored in the receive fifo can be written in 8- or 16-bit accesses. nevertheless if the user wants to transfer an odd number of bytes the last access to the transmit fifo register must be a byte access. port status and fifo operations can be accessed via register ppsr and register phnd. data written to the transmit fifo is sent starting with bit 0 up to bit 15. 15 7 0 xfifo(15:0) 0 0 0 0 0 0 0 0xfifo(7:0)
peb 3445 e register description data sheet 177 2001-06-29 ppsr hdlc port status register access : read address : 98 h reset value : 2000 h xfw transmit fifo write enable this bit indicates that data can be written to xff.xfifo. this bit is for polling use with the same meaning as the ?transmit pool ready? interrupt vector. rbc receive byte count this bit field indicates the amount of data stored in the receive fifo. valid after a ?receive message end? interrupt vector is generated. receive byte count will be cleared, when a ?receive message clear? command is executed via register hnd. note: a zero byte count in combination with a ?receive pool full? or ?receive message end? interrupt vector means that 32 bytes are available in the receive fifo. however evaluating rbc is not necessary when the ?receive pool full? interrupt was received. 15141312 87654 0 0 0 xfw rbc(4:0) - - 0 stat(4:0)
peb 3445 e register description data sheet 178 2001-06-29 stat receive fifo status this bit field reports the status of the data stored in the receive fifo. 00000 b valid hdlc frame this status is reported whenever a valid frame with valid crc was received. 00001 b receive data overflow this status indicates a receive buffer overflow while the frame was received. 00010 b receive abort indicates a frame which was aborted while being received. 00011 b not octet the frame length is not a multiple of eight bits. 00100 b crc error hdlc frame was received with crc error. 00101 b channel off this status is generated when the receiver was disabled while a frame was being received. it reports the first ?7e? flag which was received after the receiver was disabled.
peb 3445 e register description data sheet 179 2001-06-29 phnd hdlc handshake register access : write address : 9a h reset value : 0000 h note: receive command (bit 8) and transmit commands (bit 5 down to bit 0) can not be issued at the same time. doing so will cause the facility data link to omit the transmit commands. rmc receive message complete this bit is a confirmation from cpu that a data block has been read from rfifo following a ?receive pool full? or ?receive message end? interrupt vector and that the occupied page can now be released. note: if this bit is set, the low byte (transmit commands) of the register hnd is ignored. 0 no function 1 release page of receive fifo. abort abort frame setting this bit aborts hdlc frames which are transmitted. 0 normal operation 1 abort hdlc frame. xres transmitter reset this bit resets the signalling controller transmit. however, the contents of the control register will not be reset. 0 normal operation 1 transmitter reset 15 8 654 210 0 0 0 0 0 0 0rmc 0 abort xres 0 0xhf0xme
peb 3445 e register description data sheet 180 2001-06-29 xhf transmit hdlc frame setting this bit indicates that the contents written to xff.xfifo shall be transmitted as hdlc frame. if data written to xff.xfifo completes a hdlc frame, bit xme must be set together with xhf in order to generate crc and flag. 0 no function 1 transmit data stored in xff.xfifo in hdlc format. xme transmit message end setting this bit indicates that the last data block written to xff.xfifo completes the current frame. the signalling controller terminates the transmission properly by appending crc and the closing flag to the data sequence. table 9 path maintenance transmit commands xres xhf xme function 1- - reset port 010 start transmission send fifo content. this command has to be issued in case frames are longer than 32 bytes. in case frames length is equal to or smaller than 32 bytes the command ?end transmission? is sufficient. 011 end transmission send fifo content. crc (if enabled) and flag are sent after the last byte which was stored in the transmit fifo was sent.
peb 3445 e register description data sheet 181 2001-06-29 pmsk interrupt mask register access : read/write address : 9c h reset value : 00 h for each facility data link interrupt vector an interrupt vector generation mask is provided. generation of an interrupt vector itself does not necessarily result in assertion of the interrupt pin. for description of interrupt concept refer to section ?interrupt interface? on page 62 . the following definition applies: 1 the corresponding interrupt vector will not be generated by the device. 0 the corresponding interrupt vector will be generated. facility data link interrupt vector transmit alls mask ?all sent? xdu mask ??transmit data underrun? xpr mask ?transmit pool ready? facility data link interrupt vector receive rpf mask ?receive pool full? rme mask ?receive message end? 7 543210 0 0 alls xdu xpr rpf rme 0
peb 3445 e electrical characteristics data sheet 182 2001-06-29 8 electrical characteristics 8.1 important electrical requirements both v dd3 and v dd25 can take on any power-on sequence. within 50 milliseconds of power-up the voltages must be within their respective absolute voltage limits. at power- down, within 50 milliseconds of either voltage going outside its operational range, both voltages must be returned below 0.1v. 8.2 absolute maximum ratings table 10 absolute maximum ratings note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol limit values unit min max ambient temperature under bias t a -40 85 c junction temperature under bias t j 125 c storage temperature t stg -65 125 c voltage on any pin with respect to ground v s -0.4 v dd3 +0.4 v
peb 3445 e electrical characteristics data sheet 183 2001-06-29 8.3 dc characteristics a) power supply pins table 11 dc characteristics b) interface pins table 12 dc characteristics t a = -40 to 85 c, v dd3 = 3.3 v 0.3 v, v dd25 = 2.5 v + 0.25 v - 0.125 v, v ss = 0 v parameter symbol limit values unit test condition min. typ. max. core supply voltage v dd25 2.375 2.5 2.75 v i/o supply voltage v dd3 3.0 3.3 3.6 v core supply current v dd25 operational i cc25 75 100 ma power down (no clocks) i ccpd25 100 a i/o supply current v dd3 operational i cc3 45 70 ma inputs at v ss / v dd3 no output loads. power down (no clocks) i ccpd3 200 a input leakage for each pin: input leakage low input leakage high input leakage low bscan input leakage high bscan i il i ih i iil_bs i iih_bs -1 -200 5 5 a v dd25 = v dd3 =max v in =0v; v in =3.6v; v in =0v; v in =3.6v; power dissipation p 340 mw parameter symbol limit values unit test condition min. max. l-input voltage v il -0.4 0.8 v h-input voltage v ih 2.0 v dd3 +0.4 v l-output voltage v ol 0.45 v i ql = 2 ma h-output voltage v oh 2.4 v i qh = -400 a
peb 3445 e electrical characteristics data sheet 184 2001-06-29 8.4 ac characteristics t a = -40 to 85 c, v dd3 = 3.3 v 0.3 v, v dd25 = 2.5 v + 0.25 v - 0.125 v, v ss = 0 v inputs are driven to 2.4 v for a logical ?1? and to 0.4 v for a logical ?0?. timing measurements are made at 2.0 v for a logical ?1? and at 0.8 v for a logical ?0?. the ac testing input/output waveforms are shown below. ? figure 23 input/output waveform for ac tests device under test 2.0 0.8 0.8 2.0 test points 0.45 2.4 c load = 50pf
peb 3445 e electrical characteristics data sheet 185 2001-06-29 8.4.1 local microprocessor interface timing 8.4.1.1 intel bus interface timing ? figure 24 intel demultiplexed bus timing la lcs lrd ld 28 20 30 31 21 32 29 lbhe 20 21 la lcs lwr ld 28 20 21 29 lbhe 20 21 34 33 p read cycle p write cycle
peb 3445 e electrical characteristics data sheet 186 2001-06-29 ? figure 25 intel multiplexed bus timing lcs lrd la ld 28 30 31 32 29 lbhe lcs lw r la ld 28 22 29 lbhe 34 33 p read cycle p write cycle lale 25 23 22 lale 23 22 24 25 24 23 22 23
peb 3445 e electrical characteristics data sheet 187 2001-06-29 figure 26 read, write control interval in demultiplexed bus mode ? figure 27 read, write control interval in multiplexed bus mode table 13 intel bus interface timing no. parameter limit values unit min. max. 20 la, lbhe to lrd , lwr setup time 10 ns 21 la, lbhe to lrd , lwr hold time 0 ns 22 la, lbhe to lale falling setup time 10 ns 23 la, lbhe to lale falling hold time 5 ns 24 lale minimum high time 15 ns 25 lale falling to lrd , lwr setup time 10 ns 28 lcs to lrd , lwr setup time 10 ns 29 lcs to lrd , lwr hold time 0 ns 30 lrd low to ld active delay 20 ns 31 lrd high to ld float delay 5 ns 32 lrd low to ld valid delay 100 ns 33 ld to lwr setup time 20 ns 34 ld to lwr hold time 5 ns 38 read, write inactive control interval 60 ns 39 read, write active control interval 100 ns lrd x lcs lwr x lcs 38 39 lrd x lcs lwr x lcs 38 39
peb 3445 e electrical characteristics data sheet 188 2001-06-29 8.4.1.2 motorola bus interface timing ? figure 28 motorola demultiplexed bus timing la lcs lds ld 50 40 52 53 41 54 51 lble 40 41 la lcs lds ld 50 40 41 51 lble 40 41 56 55 p read cycle p write cycle 48 49 lrdwr 48 49 lrdwr
peb 3445 e electrical characteristics data sheet 189 2001-06-29 ? figure 29 motorola multiplexed bus timing lcs lds 50 52 53 54 51 lble lcs lds la ld 50 51 lble 56 55 p read cycle p write cycle lale 45 44 lale 44 48 49 lrdwr 48 49 lrdwr 43 42 la ld 43 42 42 43 42 43 45
peb 3445 e electrical characteristics data sheet 190 2001-06-29 ? figure 30 read, write control interval in demultiplexed bus mode figure 31 read, write, ale control interval in multiplexed bus mode table 14 motorola bus interface timing no. parameter limit values unit min. max. 40 la to lds setup time 10 ns 41 la to lds hold time 0 ns 42 la to lale falling setup time 10 ns 43 la to lale falling hold time 5 ns 44 lale minimum high time 15 ns 45 lale falling to lcs setup time 10 ns 48 lrdwr to lds setup time 10 ns 49 lrdwr to lds hold time 5 ns 50 lcs to lds setup time 10 ns 51 lcs to lds hold time 0 ns 52 lds low to ld active delay 20 ns 53 lds high to ld float delay 5 ns 54 lds low to ld valid delay 100 ns 55 ld to lds setup time 20 ns 56 ld to lds hold time 5 ns 58 read, write inactive control interval 60 ns 59 read, write active control interval 100 ns lcs x lds 58 59 58 59 lcs x lds lale
peb 3445 e electrical characteristics data sheet 191 2001-06-29 8.4.2 dma interface signals 8.4.2.1 dma receive timing figure 32 dma receive timing note: 1 intel mode 2 motorola mode 3 drr is asserted asynchronously as soon as there is data in the receive fifo. 4rmc is asserted when the last data belonging to a message was read. table 15 dma receive timing no. parameter limit values unit min. max. 60 lrd , lds inactive to drr inactive delay ns 61 lrd , lds inactive to rmc active delay ns 62 lrd , lds inactive to rmc inactive delay ns lrd 1 lds 2 drr 3 rmc 4 61 62 60
peb 3445 e electrical characteristics data sheet 192 2001-06-29 8.4.2.2 dma transmit timing figure 33 dma transmit timing note: 1 intel mode 2 motorola mode 3 drt is asserted asynchronously as soon as there is free space in the transmit fifo. 4txme has to be asserted while the last byte of a message is written to the transmit fifo. table 16 dma transmit timing no. parameter limit values unit min. max. 65 lrd , lds inactive to drt inactive delay ns 66 txme to lds setup time 20 ns 67 txme to lds hold time 5 ns lwr 1 lds 2 drt 3 txme 4 65 67 66
peb 3445 e electrical characteristics data sheet 193 2001-06-29 8.4.3 serial interface timing 8.4.3.1 ds3 serial interface timing ? figure 34 clock input timing table 17 clock input timing no. parameter limit values unit min. max. 100 clock period nom. 44.736 mhz 101 clock high timing 7.5 ns 102 clock low timing 7.5 ns 103 clock fall time 2 ns 104 clock rise time 2 ns tclk44 rclk44 100 101 102 103 104
peb 3445 e electrical characteristics data sheet 194 2001-06-29 ? figure 35 ds3 transmit cycle timing note: 1. actual clock reference depends on selected clock mode: ? figure 36 ds3 transmit data timing note: 2. timing for transmit data which is updated on the rising edge of tclko44. 3. timing for transmit data which is updated on the falling edge of tclko44. table 18 ds3 transmit cycle timing no. parameter limit values unit min. max. 110 rclk44, tclk44 to tclko44 delay 2 15 ns 111 tclko44 to td44, td44p/td44n delay 0 5 ns 110 110 tclk44 rclk44 (note 1) tclko44 111 td44, td44p/n tclko44 (note 2) tclko44 (note 3)
peb 3445 e electrical characteristics data sheet 195 2001-06-29 ? figure 37 ds3 receive cycle timing note: 1. timing for data which is sampled on the rising edge of the receive clock. 2. timing for data which is sampled on the falling edge of the receive clock. table 19 ds3 receive cycle timing ? no. parameter limit values unit min. max. 130 rd44, rd44p, rd44n to rclk44 setup time 5 ns 131 rd44, rd44p, rd44n to rclk44 hold time 5 ns 130 131 rclk44 (note 1) rd44, rd44p/n rclk44 (note 2)
peb 3445 e electrical characteristics data sheet 196 2001-06-29 8.4.3.2 overhead bit timing ? figure 38 ds3 transmit overhead timing ? figure 39 ds3 transmit overhead synchronization timing table 20 ds3 transmit overhead timing no. parameter limit values unit min. max. 150 tovhck to tovhsyn delay 75 ns 151 tovhsyn to tclko44 setup time 7 ns 152 tovhsyn to tclko44 hold time 7 ns 153 tovhd to tovhck setup time 25 ns 154 tovhd to tovhck hold time 5 ns 155 tovhden to tovhck setup time 25 ns 156 tovhden to tovhck hold time 5 ns tovhsyn (output mode)) tovhd tovhck 155 156 tovhden 153 154 150 tclko44 tovhsyn (input mode) 151 152
peb 3445 e electrical characteristics data sheet 197 2001-06-29 ? figure 40 ds3 receive overhead timing table 21 ds3 receive overhead timing no. parameter limit values unit min. max. 157 rovhck to rovhsyn delay 75 ns 158 rovhck to rovhd delay 75 ns 157 rovhsyn rovhd rovhck 158
peb 3445 e electrical characteristics data sheet 198 2001-06-29 8.4.3.3 stuff bit timing ? figure 41 ds3 transmit stuff bit timing table 22 ds3 transmit stuff timing ? figure 42 ds3 receive stuff bit timing table 23 ds3 receive stuff bit timing no. parameter limit values unit min. max. 160 tsbd to tsbck setup time 25 ns 161 tsbd to tsbck hold time 5 ns no. parameter limit values unit min. max. 162 rsbck to rsbd delay 75 ns tsbck 160 161 tsbd 162 rsbd rsbck
peb 3445 e electrical characteristics data sheet 199 2001-06-29 8.4.3.4 ds1/e1 interface timing ? figure 43 ds1/e1 transmit clock timing table 24 ds1/e1 transmit clock timing no. parameter limit values unit min. typ max. interface operated in e1 mode 170 clock period 2.048 mhz 50 ppm 171 clock high timing 100 ns 172 clock low timing 100 ns 173 clock fall time 10 ns 174 clock rise time 10 ns interface operated in ds1 mode 170 clock period 1.544 mhz 130 ppm 171 clock high timing 100 ns 172 clock low timing 100 ns 173 clock fall time 10 ns 174 clock rise time 10 ns ttc(x) 170 171 172 173 174
peb 3445 e electrical characteristics data sheet 200 2001-06-29 ? figure 44 ds1/e1 transmit data timing note: 1. timing for transmit data sampled on the rising edge of ttc(x). 2. timing for transmit data sampled on the falling edge of ttc(x). table 25 ds1/e1 transmit data timing no. parameter limit values unit min. max. 175 ttd(x) to ttc(x) setup time 25 ns 176 ttd(x) to ttc(x) hold time 75 ns 175 176 ttc(x) (note 1) ttd(x) ttc(x) (note 2)
peb 3445 e electrical characteristics data sheet 201 2001-06-29 ? figure 45 ds1/e1 receive clock timing table 26 ds1/e1 receive clock timing no. parameter limit values unit min. typ max. interface operated in e1 mode 180 clock period 469 2056 ns 181 clock high timing 156 335 ns 182 clock low timing 312 1900 ns interface operated in ds1 mode 180 clock period 625 1587 ns 181 clock high timing 310 495 ns 182 clock low timing 310 1275 ns rtc(x) 180 181 182
peb 3445 e electrical characteristics data sheet 202 2001-06-29 ? figure 46 ds1/e1 receive data timing note: 1. timing for receive data updated on the rising edge of rtc(x). 2. timing for receive data updated on the falling edge of rtc(x). table 27 ds1/e1 receive data timing no. parameter limit values unit min. max. 185 rtc(x) to rtd(x) delay 25 75 ns 185 rtd(x) rtc(x) (note 1) rtc(x) (note 2)
peb 3445 e electrical characteristics data sheet 203 2001-06-29 8.4.3.5 ds3 system interface timing ? figure 47 ds3 system clock timing table 28 ds3 system clock timing figure 48 ds3 system transmit data timing table 29 ds3 system transmit data timing no. parameter limit values unit min. typ max. 190 clock period 22.35 44.7 ns 191 clock high timing 7.5 ns 192 clock low timing 7.5 ns no. parameter limit values unit min. max. 195 ttd(1) to ttc(1) setup time 7 ns 196 ttd(1) to ttc(1) hold time 5 ns rtc(1) ttc(1) 190 191 192 195 196 ttc(1) ttd(1)
peb 3445 e electrical characteristics data sheet 204 2001-06-29 figure 49 ds3 system receive data timing table 30 ds3 system receive data timing no. parameter limit values unit min. max. 198 rtc(1) to rtd(1) delay -5 7 ns 198 rtd(1) rtc(1)
peb 3445 e electrical characteristics data sheet 205 2001-06-29 8.4.4 jtag interface timing ? figure 50 jtag interface timing table 31 jtag interface timing no. parameter limit values unit min. max. 200 tck period 120 ns 201 tck high time 60 ns 202 tck low time 60 ns 203 tms setup time 20 ns 204 tms hold time 20 ns 205 tdi setup time 20 ns 206 tdi hold time 20 ns 207 tdo valid time 50 ns trst tck tms tdi tdo 202 201 200 203 204 205 206 207
peb 3445 e electrical characteristics data sheet 206 2001-06-29 8.4.5 reset timing ? figure 51 reset timing table 32 reset timing no. parameter limit values unit min. max. 220 rst pulse width 1 s v dd3 v dd25 220 rst power-on vdd3 and vdd25 are up and in their respective limits
peb 3445 e package outline data sheet 207 2001-06-29 9 package outline
peb 3445 e package outline data sheet 208 2001-06-29
peb 3445 e package outline data sheet 209 2001-06-29
peb 3445 e package outline data sheet 210 2001-06-29
qualit?t hat fr uns eine umfassende bedeutung. wir wollen allen ihren ansprchen in der bestm?glichen weise gerecht werden. es geht uns also nicht nur um die produktqualit?t ? unsere anstrengungen gelten gleicherma?en der lieferqualit?t und logistik, dem service und support sowie allen sonstigen beratungs- und betreuungsleistungen. dazu geh?rt eine bestimmte geisteshaltung unserer mitarbeiter. total quality im denken und handeln gegenber kollegen, lieferanten und ihnen, unserem kunden. unsere leitlinie ist jede aufgabe mit ?null fehlern? zu l?sen ? in offener sichtweise auch ber den eigenen arbeitsplatz hinaus ? und uns st?ndig zu verbessern. unternehmensweit orientieren wir uns dabei auch an ?top? (time optimized processes), um ihnen durch gr??ere schnelligkeit den entscheidenden wettbewerbsvorsprung zu verschaffen. geben sie uns die chance, hohe leistung durch umfassende qualit?t zu beweisen. wir werden sie berzeugen. quality takes on an allencompassing significance at semiconductor group. for us it means living up to each and every one of your demands in the best possible way. so we are not only concerned with product quality. we direct our efforts equally at quality of supply and logistics, service and support, as well as all the other ways in which we advise and attend to you. part of this is the very special attitude of our staff. total quality in thought and deed, towards co-workers, suppliers and you, our customer. our guideline is ?do everything with zero defects?, in an open manner that is demonstrated beyond your immediate workplace, and to constantly improve. throughout the corporation we also think in terms of time optimized processes (top), greater speed on our part to give you that decisive competitive edge. give us the chance to prove the best of performance through the best of quality ? you will be convinced. http://www.infineon.com total quality management published by infineon technologies ag

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